mirror of
https://github.com/SDL-Hercules-390/hyperion.git
synced 2026-04-10 22:24:32 +02:00
231 lines
11 KiB
C
231 lines
11 KiB
C
/* QDIO.H (c) Copyright Jan Jaeger, 2010-2012 */
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/* Queued Direct I/O */
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/* This implementation is based on the S/390 Linux implementation */
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#if !defined(_QDIO_H)
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#define _QDIO_H
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/*-------------------------------------------------------------------*/
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/* OSA Device Structure */
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/*-------------------------------------------------------------------*/
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typedef struct _QDIO_DEV {
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unsigned rxcnt; /* Receive count */
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unsigned txcnt; /* Transmit count */
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int idxstate; /* IDX state */
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#define MPC_IDX_STATE_INACTIVE 0x00 // ZZ THIS FIELD NEEDS TO MOVE
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#define MPC_IDX_STATE_ACTIVE 0x01
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#define MPC_IDX_STATE_HALTING 0x02
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int thinint; /* Thin Interrupts on PCI */
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int i_qcnt; /* Input Queue Count */
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int i_qpos; /* Current Queue Position */
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int i_bpos[QDIO_MAXQ]; /* Current Buffer Position */
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int o_qcnt; /* Output Queue Count */
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int o_qpos; /* Current Queue Position */
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int o_bpos[QDIO_MAXQ]; /* Current Buffer Position */
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U32 i_qmask; /* Input Queue Mask */
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U32 o_qmask; /* Output Queue Mask */
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BYTE i_slibk[QDIO_MAXQ]; /* Input SLIB Key */
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BYTE i_slk[QDIO_MAXQ]; /* Input Storage List Key */
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BYTE i_sbalk[QDIO_MAXQ]; /* Input SBAL Key */
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BYTE i_slsblk[QDIO_MAXQ]; /* Input SLSB Key */
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U64 i_sliba[QDIO_MAXQ]; /* Input SLIB Address */
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U64 i_sla[QDIO_MAXQ]; /* Input Storage List Address */
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U64 i_slsbla[QDIO_MAXQ]; /* Input SLSB Address */
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BYTE o_slibk[QDIO_MAXQ]; /* Output SLIB Key */
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BYTE o_slk[QDIO_MAXQ]; /* Output Storage List Key */
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BYTE o_sbalk[QDIO_MAXQ]; /* Output SBAL Key */
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BYTE o_slsblk[QDIO_MAXQ]; /* Output SLSB Key */
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U64 o_sliba[QDIO_MAXQ]; /* Output SLIB Address */
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U64 o_sla[QDIO_MAXQ]; /* Output Storage List Address */
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U64 o_slsbla[QDIO_MAXQ]; /* Output SLSB Address */
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BYTE qibk; /* Queue Information Block Key */
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U64 qiba; /* Queue Information Block Address */
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U64 alsi; /* Adapter Local Summary Indicator */
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#define ALSI_ERROR 0x80 /* ZZ TO BE CONFIRMED */
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U64 dsci; /* Device status change Indicator */
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#define DSCI_IOCOMP 0x01 /* ZZ TO BE CONFIRMED */
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BYTE ks; /* alsi storage key */
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BYTE kc; /* dsci storage key */
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} QDIO_DEV;
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/*-------------------------------------------------------------------*/
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/* Queue Descriptor Entry (Format 0) */
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/*-------------------------------------------------------------------*/
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typedef struct _QDIO_QDES0 {
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/*000*/ DBLWRD sliba; /* Storage List Info Block Address */
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/*008*/ DBLWRD sla; /* Storage List Address */
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/*010*/ DBLWRD slsba; /* Storage List State Block Address */
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/*018*/ FWORD resv018;
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/*01C*/ BYTE keyp1; /* Access keys for SLIB and SL */
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#define QDES_KEYP1_A_SLIB 0xF0
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#define QDES_KEYP1_A_SL 0x0F
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/*01D*/ BYTE keyp2; /* Access keys for SBALs ad SLSB */
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#define QDES_KEYP2_A_SBAL 0xF0
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#define QDES_KEYP2_A_SLSB 0x0F
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/*01E*/ HWORD resv01e;
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} QDIO_QDES0;
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/*-------------------------------------------------------------------*/
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/* Queue Descriptor Record (QDR) */
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/*-------------------------------------------------------------------*/
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typedef struct _QDIO_QDR {
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/*000*/ BYTE qfmt; /* Queue Format */
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/*001*/ BYTE pfmt; /* Model Dependent Parameter Format */
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/*002*/ BYTE resv002;
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/*003*/ BYTE ac; /* Adapter Characteristics */
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/*004*/ BYTE resv004;
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/*005*/ BYTE iqdcnt; /* Input Queue Descriptor Count */
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/*006*/ BYTE resv006;
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/*007*/ BYTE oqdcnt; /* Output Queue Descriptor Count */
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/*008*/ BYTE resv008;
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/*009*/ BYTE iqdsz; /* Input Queue Descriptor Size */
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/*00A*/ BYTE resv00a;
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/*00B*/ BYTE oqdsz; /* Output Queue Descriptor Size */
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/*00C*/ FWORD resv00c[9];
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/*030*/ DBLWRD qiba; /* Queue Information Block Address */
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/*038*/ FWORD resv038;
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/*03C*/ BYTE qkey; /* Queue Information Block Key */
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/*03D*/ BYTE resv03d[3];
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/*040*/ QDIO_QDES0 qdf0[126]; /* Format 0 Queue Descriptors */
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} QDIO_QDR;
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/*-------------------------------------------------------------------*/
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/* Queue Information Block (QIB) */
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/*-------------------------------------------------------------------*/
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typedef struct _QDIO_QIB {
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/*000*/ BYTE qfmt; /* Queue Format */
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/*001*/ BYTE pfmt; /* Parameter Format */
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#define QID_PFMT_QETH 0x00
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/*002*/ BYTE rflags; /* Flags */
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#define QIB_RFLAGS_QEBSM 0x80
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/*003*/ BYTE ac; /* Adapter Characteristics */
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#define QIB_AC_PCI 0x40
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/*004*/ FWORD resv004;
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/*008*/ DBLWRD isliba; /* Input SLIB queue address */
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/*010*/ DBLWRD osliba; /* Output SLIB queue address */
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/*018*/ FWORD resv018;
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/*01C*/ FWORD resv01c;
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/*020*/ BYTE ebcnam[8]; /* Adapter ID in EBCDIC */
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/*028*/ BYTE resv028[88];
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/*080*/ BYTE parm[128]; /* Model Dependent Parameters */
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} QDIO_QIB;
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/*-------------------------------------------------------------------*/
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/* Maximum number of Storage array entries */
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/*-------------------------------------------------------------------*/
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#define QMAXBUFS 128 /* Maximum Number of Buffers */
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#define QMAXSTBK 16 /* Maximum Storage block entries */
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/*-------------------------------------------------------------------*/
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/* Storage List Information Block (SLIB) */
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/*-------------------------------------------------------------------*/
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typedef struct _QDIO_SLIB {
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/*000*/ DBLWRD nsliba; /* Next SLIB in queue */
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/*008*/ DBLWRD sla; /* Storage List Address */
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/*010*/ DBLWRD slsba; /* Storage List State Block Address */
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/*018*/ BYTE resv018[1000];
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/*400*/ DBLWRD slibe[QMAXBUFS];/* Storage List Info. Block Entries */
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} QDIO_SLIB;
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/*-------------------------------------------------------------------*/
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/* Storage List (SL) */
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/*-------------------------------------------------------------------*/
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typedef struct _QDIO_SL {
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/*000*/ DBLWRD sbala[QMAXBUFS];/* Storage Block Address List address*/
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} QDIO_SL;
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/*-------------------------------------------------------------------*/
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/* Storage Block Address List Entry (SBALE) */
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/*-------------------------------------------------------------------*/
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typedef struct _QDIO_SBALE {
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/*000*/ BYTE flags[4]; /* Flags */
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#define SBALE_FLAG0_LAST_ENTRY 0x40
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#define SBALE_FLAG0_CONTIGUOUS 0x20
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#define SBALE_FLAG0_FRAG_MASK 0x0C
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#define SBALE_FLAG0_FRAG_FIRST 0x04
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#define SBALE_FLAG0_FRAG_MIDDLE 0x08
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#define SBALE_FLAG0_FRAG_LAST 0x0C
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#define SBALE_FLAG3_PCI_REQ 0x40
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/*004*/ FWORD length; /* Storage length */
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/*008*/ DBLWRD addr; /* Storage Address */
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} QDIO_SBALE;
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/*-------------------------------------------------------------------*/
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/* Storage Block Address List (SBAL) */
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/*-------------------------------------------------------------------*/
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typedef struct _QDIO_SBAL {
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/*000*/ QDIO_SBALE sbale[QMAXSTBK];/* Storage Block Addr. List entry */
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} QDIO_SBAL;
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/*-------------------------------------------------------------------*/
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/* Storage List State Block (SLSB) */
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/*-------------------------------------------------------------------*/
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typedef struct _QDIO_SLSB {
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/*000*/ BYTE slsbe[QMAXBUFS];/* Storage Block Address List entry */
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#define SLSBE_OWNER 0xC0 /* Owner Mask */
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#define SLSBE_OWNER_OS 0x80 /* Control Program is owner */
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#define SLSBE_OWNER_CU 0x40 /* Control Unit is owner */
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#define SLSBE_TYPE 0x20 /* Buffer type mask */
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#define SLSBE_TYPE_INPUT 0x00 /* Input Buffer */
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#define SLSBE_TYPE_OUTPUT 0x20 /* Output Buffer */
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#define SLSBE_VALID 0x10 /* Buffer Valid */
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#define SLSBE_STATE 0x0F /* Buffer state mask */
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#define SLSBE_STATE_NOTINIT 0x00 /* Not initialised */
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#define SLSBE_STATE_EMPTY 0x01 /* Buffer empty */
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#define SLSBE_STATE_PRIMED 0x02 /* Buffer ready */
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#define SLSBE_STATE_PENDING 0x03 /* Buffer pending */
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#define SLSBE_STATE_HALTED 0x0E /* I/O halted */
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#define SLSBE_STATE_ERROR 0x0F /* I/O Error */
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#define SLSBE_ERROR 0xFF /* Addressing Error */
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#define SLSBE_OUTPUT_PRIMED ( 0 \
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| SLSBE_OWNER_CU \
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| SLSBE_TYPE_OUTPUT \
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| SLSBE_STATE_PRIMED \
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)
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#define SLSBE_OUTPUT_COMPLETED ( 0 \
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| SLSBE_OWNER_OS \
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| SLSBE_TYPE_OUTPUT \
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| SLSBE_STATE_EMPTY \
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)
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#define SLSBE_INPUT_EMPTY ( 0 \
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| SLSBE_OWNER_CU \
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| SLSBE_TYPE_INPUT \
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| SLSBE_STATE_EMPTY \
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)
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#define SLSBE_INPUT_ACKED ( 0 \
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| SLSBE_OWNER_OS \
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| SLSBE_TYPE_INPUT \
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| SLSBE_STATE_EMPTY \
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)
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#define SLSBE_INPUT_COMPLETED ( 0 \
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| SLSBE_OWNER_OS \
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| SLSBE_TYPE_INPUT \
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| SLSBE_STATE_PRIMED \
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)
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} QDIO_SLSB;
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#endif /*!defined(_QDIO_H)*/
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