mirror of
https://github.com/SDL-Hercules-390/hyperion.git
synced 2026-04-18 01:40:25 +02:00
129 lines
5.6 KiB
Plaintext
129 lines
5.6 KiB
Plaintext
* CGXR test
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sysclear
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archmode esame
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r 1a0=00000001800000000000000000000200 # z/Arch restart PSW
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r 1d0=00020001800000000000000000BADBAD # z/Arch pgm new PSW
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r 200=B7000330 # LCTL R0,R0,CTLR0 Set CR0 bit 45
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r 204=B29D0334 # LFPC FPCREG Load FPC register
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r 208=41000008 # LA R0,8 R0=Number of test data
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r 20C=41100800 # LA R1,TEST1 R1=>Test data table
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r 210=41F00900 # LA R15,RES1 R15=>Result table
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r 214=68401000 #A LD F4,0(,R1) Load FPR4=TESTn (high)
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r 218=68601008 # LD F6,8(,R1) Load FPR6=TESTn (low)
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r 21C=41200000 # LA R2,X'00' R2=Rounding mode
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r 220=42200232 #B STC R2,I+2 Store rounding mode into instr
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r 224=E54C008C0000 # MVHI PGMINTC,0 Clear PGM check interrupt code
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r 22A=D20F01D00320 # MVC PGMNPSW,NEWPSWI Set program check new PSW
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r 230=B3CA0074 # CXGR R7,0,F4 Convert FPR4,FPR6 into R7
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r 234=D20F01D00310 # MVC PGMNPSW,DISWAIT Restore program check new PSW
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r 23A=B2220080 # IPM R8 R8=Cond code and pgm mask
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r 23E=5890008C # L R9,PGMINTC R9=PGM check interrupt code
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r 242=E370F0000024 # STG R7,0(,R15) Store R7 in result table
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r 248=9089F008 # STM R8,R9,8(R15) Store CC and PIC in table
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r 24C=41F0F010 # LA R15,16(,R15) R15=>next result table
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r 250=EC270005107F # CLIJNE R2,X'10',*+10 Skip if not rounding mode 1
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r 256=41202020 # LA R2,X'20'(R2) Bypass rounding modes 2 and 3
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r 25A=41202010 # LA R2,X'10'(R2) R2=Next rounding mode
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r 25E=EC24022080FF # CLIBL R2,X'80',B Loop if rounding mode less than 8
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r 264=41101010 # LA R1,16(,R1) R1=>Next TESTn
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r 268=46000214 # BCT R0,A Loop to end of TEST table
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r 26C=41000900 # LA R0,RES1 R0->Actual results
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r 270=41100300 # LA R1,48*16 R1=Length of results table
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r 274=41200C00 # LA R2,EXP1 R2->Expected results
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r 278=41300300 # LA R3,48*16 R3=Length of results table
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r 27C=0F02 # CLCL R0,R2 Compare with expected results
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r 27E=477002FC # BNE DIE Error if not equal
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r 282=B2B20300 # LPSWE WAITPSW Load enabled wait PSW
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r 2FC=B2B20310 # LPSWE DISWAIT Load disabled wait PSW
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r 300=07020001800000000000000000AAAAAA # WAITPSW Enabled wait state PSW
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r 310=00020001800000000000000000BADBAD # DISWAIT Disabled wait state PSW
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r 320=00000001800000000000000000000340 # NEWPSWI New PSW for PGMFLIH
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r 330=00040000 # CTLR0 Control register 0 (bit45 AFP control)
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r 334=00000000 # FPCREG Floating point control register
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r 340=B2B20150 #PGMFLIH LPSWE PGMOPSW Program check interrupt handler
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r 800=D080000000000000C200800000000000 # TEST1 DC LH'-9223372036854775808.5'
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r 810=C880000000800000BA00000000000000 # TEST2 DC LH'-2147483648.5'
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r 820=C27B800000000000B400000000000000 # TEST3 DC LH'-123.5'
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r 830=80000000000000008000000000000000 # TEST4 DC LH'-0'
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r 840=427A8000000000003400000000000000 # TEST5 DC LH'122.5'
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r 850=487FFFFFFFC000003A00000000000000 # TEST6 DC LH'2147483647.75'
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r 860=507FFFFFFFFFFFFF42FF400000000000 # TEST7 DC LH'9223372036854775807.25'
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r 870=507FFFFFFFFFFFFF42FF800000000000 # TEST8 DC LH'9223372036854775807.5'
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* Expected results - TEST1
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r C00=80000000000000001000000000000000 # RM=0 Round toward 0
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r C10=80000000000000003000000000000000 # RM=1 Round nearest ties away from 0
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r C20=80000000000000001000000000000000 # RM=4 Round nearest ties to even
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r C30=80000000000000001000000000000000 # RM=5 Round toward 0
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r C40=80000000000000001000000000000000 # RM=6 Round toward +INF
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r C50=80000000000000003000000000000000 # RM=7 Round toward -INF
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* Expected results - TEST2
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r C60=FFFFFFFF800000001000000000000000
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r C70=FFFFFFFF7FFFFFFF1000000000000000
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r C80=FFFFFFFF800000001000000000000000
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r C90=FFFFFFFF800000001000000000000000
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r CA0=FFFFFFFF800000001000000000000000
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r CB0=FFFFFFFF7FFFFFFF1000000000000000
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* Expected results - TEST3
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r CC0=FFFFFFFFFFFFFF851000000000000000
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r CD0=FFFFFFFFFFFFFF841000000000000000
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r CE0=FFFFFFFFFFFFFF841000000000000000
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r CF0=FFFFFFFFFFFFFF851000000000000000
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r D00=FFFFFFFFFFFFFF851000000000000000
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r D10=FFFFFFFFFFFFFF841000000000000000
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* Expected results - TEST4
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r D20=00000000000000000000000000000000
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r D30=00000000000000000000000000000000
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r D40=00000000000000000000000000000000
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r D50=00000000000000000000000000000000
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r D60=00000000000000000000000000000000
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r D70=00000000000000000000000000000000
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* Expected results - TEST5
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r D80=000000000000007A2000000000000000
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r D90=000000000000007B2000000000000000
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r DA0=000000000000007A2000000000000000
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r DB0=000000000000007A2000000000000000
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r DC0=000000000000007B2000000000000000
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r DD0=000000000000007A2000000000000000
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* Expected results - TEST6
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r DE0=000000007FFFFFFF2000000000000000
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r DF0=00000000800000002000000000000000
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r E00=00000000800000002000000000000000
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r E10=000000007FFFFFFF2000000000000000
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r E20=00000000800000002000000000000000
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r E30=000000007FFFFFFF2000000000000000
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* Expected results - TEST7
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r E40=7FFFFFFFFFFFFFFF2000000000000000
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r E50=7FFFFFFFFFFFFFFF2000000000000000
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r E60=7FFFFFFFFFFFFFFF2000000000000000
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r E70=7FFFFFFFFFFFFFFF2000000000000000
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r E80=7FFFFFFFFFFFFFFF3000000000000000
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r E90=7FFFFFFFFFFFFFFF2000000000000000
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* Expected results - TEST8
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r EA0=7FFFFFFFFFFFFFFF2000000000000000
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r EB0=7FFFFFFFFFFFFFFF3000000000000000
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r EC0=7FFFFFFFFFFFFFFF3000000000000000
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r ED0=7FFFFFFFFFFFFFFF2000000000000000
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r EE0=7FFFFFFFFFFFFFFF3000000000000000
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r EF0=7FFFFFFFFFFFFFFF2000000000000000
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ostailor null
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restart
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pause 1
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* Display test data
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r 800.80
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* Display results - TEST1
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r 900.60
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* Display results - TEST2
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r 960.60
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* Display results - TEST3
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r 9C0.60
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* Display results - TEST4
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r A20.60
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* Display results - TEST5
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r A80.60
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* Display results - TEST6
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r AE0.60
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* Display results - TEST7
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r B40.60
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* Display results - TEST8
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r BA0.60
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