mirror of
https://github.com/SDL-Hercules-390/hyperion.git
synced 2026-05-24 11:07:38 +02:00
Jan Jaeger
ba3a5f7811
git-svn-id: file:///home/jj/hercules.svn/trunk@670 956126f8-22a0-4046-8f4a-272fa8102e63
1041 lines
32 KiB
C
1041 lines
32 KiB
C
/* IO.C (c) Copyright Roger Bowler, 1994-2002 */
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/* ESA/390 CPU Emulator */
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/* Interpretive Execution - (c) Copyright Jan Jaeger, 1999-2002 */
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/* z/Architecture support - (c) Copyright Jan Jaeger, 1999-2002 */
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/*-------------------------------------------------------------------*/
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/* This module implements all I/O instructions of the */
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/* S/370 and ESA/390 architectures, as described in the manuals */
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/* GA22-7000-03 System/370 Principles of Operation */
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/* SA22-7201-06 ESA/390 Principles of Operation */
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/*-------------------------------------------------------------------*/
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/*-------------------------------------------------------------------*/
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/* Additional credits: */
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/* STCPS and SCHM instructions by Jan Jaeger */
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/* STCRW instruction by Jan Jaeger */
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/* Instruction decode by macros - Jan Jaeger */
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/* Instruction decode rework - Jan Jaeger */
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/* Correct nullification of TIO and TSCH - Jan Jaeger */
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/* Lock device during MSCH update - Jan Jaeger */
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/* SIE support - Jan Jaeger */
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/* SAL instruction added - Jan Jaeger */
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/* RCHP instruction added - Jan Jaeger */
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/* CONCS instruction added - Jan Jaeger */
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/* DISCS instruction added - Jan Jaeger */
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/* TPI fix - Jay Maynard, found by Greg Smith */
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/* STCRW instruction nullification correction - Jan Jaeger */
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/* I/O rate counter - Valery Pogonchenko */
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/* 64-bit IDAW support - Roger Bowler v209 @IWZ*/
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/*-------------------------------------------------------------------*/
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#include "hercules.h"
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#include "opcode.h"
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#include "inline.h"
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#if defined(FEATURE_CHANNEL_SUBSYSTEM)
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/*-------------------------------------------------------------------*/
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/* B230 CSCH - Clear Subchannel [S] */
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/*-------------------------------------------------------------------*/
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DEF_INST(clear_subchannel)
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{
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int b2; /* Effective addr base */
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VADR effective_addr2; /* Effective address */
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DEVBLK *dev; /* -> device block */
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S(inst, execflag, regs, b2, effective_addr2);
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PRIV_CHECK(regs);
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SIE_INTERCEPT(regs);
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/* Program check if reg 1 bits 0-15 not X'0001' */
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if ( regs->GR_LHH(1) != 0x0001 )
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ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
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/* Locate the device block for this subchannel */
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dev = find_device_by_subchan (regs->GR_LHL(1));
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/* Condition code 3 if subchannel does not exist,
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is not valid, or is not enabled */
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if (dev == NULL
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|| (dev->pmcw.flag5 & PMCW5_V) == 0
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|| (dev->pmcw.flag5 & PMCW5_E) == 0)
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{
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regs->psw.cc = 3;
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return;
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}
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/* Perform clear subchannel and set condition code zero */
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clear_subchan (regs, dev);
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regs->psw.cc = 0;
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}
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/*-------------------------------------------------------------------*/
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/* B231 HSCH - Halt Subchannel [S] */
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/*-------------------------------------------------------------------*/
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DEF_INST(halt_subchannel)
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{
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int b2; /* Effective addr base */
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VADR effective_addr2; /* Effective address */
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DEVBLK *dev; /* -> device block */
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S(inst, execflag, regs, b2, effective_addr2);
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PRIV_CHECK(regs);
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SIE_INTERCEPT(regs);
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/* Program check if reg 1 bits 0-15 not X'0001' */
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if ( regs->GR_LHH(1) != 0x0001 )
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ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
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/* Locate the device block for this subchannel */
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dev = find_device_by_subchan (regs->GR_LHL(1));
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/* Condition code 3 if subchannel does not exist,
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is not valid, or is not enabled */
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if (dev == NULL
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|| (dev->pmcw.flag5 & PMCW5_V) == 0
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|| (dev->pmcw.flag5 & PMCW5_E) == 0)
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{
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regs->psw.cc = 3;
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return;
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}
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/* Perform halt subchannel and set condition code */
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regs->psw.cc = halt_subchan (regs, dev);
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}
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/*-------------------------------------------------------------------*/
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/* B232 MSCH - Modify Subchannel [S] */
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/*-------------------------------------------------------------------*/
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DEF_INST(modify_subchannel)
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{
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int b2; /* Effective addr base */
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VADR effective_addr2; /* Effective address */
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DEVBLK *dev; /* -> device block */
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PMCW pmcw; /* Path management ctl word */
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S(inst, execflag, regs, b2, effective_addr2);
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PRIV_CHECK(regs);
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SIE_INTERCEPT(regs);
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FW_CHECK(effective_addr2, regs);
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/* Fetch the updated path management control word */
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ARCH_DEP(vfetchc) ( &pmcw, sizeof(PMCW)-1, effective_addr2, b2, regs );
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/* Program check if reserved bits are not zero */
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if (pmcw.flag4 & PMCW4_RESV
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|| (pmcw.flag5 & PMCW5_LM) == PMCW5_LM_RESV
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|| pmcw.flag24 != 0 || pmcw.flag25 != 0
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|| pmcw.flag26 != 0 || (pmcw.flag27 & PMCW27_RESV))
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ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
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/* Program check if reg 1 bits 0-15 not X'0001' */
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if ( regs->GR_LHH(1) != 0x0001 )
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ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
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/* Locate the device block for this subchannel */
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dev = find_device_by_subchan (regs->GR_LHL(1));
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/* Condition code 3 if subchannel does not exist */
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if (dev == NULL)
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{
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regs->psw.cc = 3;
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return;
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}
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/* If the subchannel is invalid then return cc0 */
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if (!(dev->pmcw.flag5 & PMCW5_V))
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{
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regs->psw.cc = 0;
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return;
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}
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/* Perform serialization and checkpoint-synchronization */
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PERFORM_SERIALIZATION (regs);
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PERFORM_CHKPT_SYNC (regs);
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/* Condition code 1 if subchannel is status pending
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with other than intermediate status */
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if ((dev->scsw.flag3 & SCSW3_SC_PEND)
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&& !(dev->scsw.flag3 & SCSW3_SC_INTER))
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{
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regs->psw.cc = 1;
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return;
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}
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/* Obtain the device lock */
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obtain_lock (&dev->lock);
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/* Condition code 2 if subchannel is busy */
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if (dev->busy || dev->pending)
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{
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regs->psw.cc = 2;
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release_lock (&dev->lock);
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return;
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}
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/* Update the enabled (E), limit mode (LM),
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and measurement mode (MM), and multipath (D) bits */
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dev->pmcw.flag5 &=
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~(PMCW5_E | PMCW5_LM | PMCW5_MM | PMCW5_D);
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dev->pmcw.flag5 |= (pmcw.flag5 &
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(PMCW5_E | PMCW5_LM | PMCW5_MM | PMCW5_D));
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/* Update the measurement block index */
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memcpy (dev->pmcw.mbi, pmcw.mbi, sizeof(HWORD));
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/* Update the interruption parameter */
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memcpy (dev->pmcw.intparm, pmcw.intparm, sizeof(FWORD));
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/* Update the interruption subclass (ISC) field */
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dev->pmcw.flag4 &= ~PMCW4_ISC;
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dev->pmcw.flag4 |= (pmcw.flag4 & PMCW4_ISC);
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/* Update the path management (LPM and POM) fields */
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dev->pmcw.lpm = pmcw.lpm;
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dev->pmcw.pom = pmcw.pom;
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/* Update the concurrent sense (S) field */
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dev->pmcw.flag27 &= ~PMCW27_S;
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dev->pmcw.flag27 |= (pmcw.flag27 & PMCW27_S);
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/* Set device priority from the interruption subclass bits */
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dev->priority = (dev->pmcw.flag4 & PMCW4_ISC) >> 3;
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release_lock (&dev->lock);
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/* Set condition code 0 */
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regs->psw.cc = 0;
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}
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/*-------------------------------------------------------------------*/
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/* B23B RCHP - Reset Channel Path [S] */
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/*-------------------------------------------------------------------*/
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DEF_INST(reset_channel_path)
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{
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int b2; /* Base of effective addr */
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VADR effective_addr2; /* Effective address */
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BYTE chpid;
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S(inst, execflag, regs, b2, effective_addr2);
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PRIV_CHECK(regs);
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SIE_INTERCEPT(regs);
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/* Program check if reg 1 bits 0-23 not zero */
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if(regs->GR_L(1) & 0xFFFFFF00)
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ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
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chpid = effective_addr2 & 0xFF;
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if( !(regs->psw.cc = chp_reset(chpid)) )
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{
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obtain_lock(&sysblk.intlock);
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sysblk.chp_reset[chpid/32] |= 0x80000000 >> (chpid % 32);
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ON_IC_CHANRPT;
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WAKEUP_WAITING_CPU (ALL_CPUS, CPUSTATE_STARTED);
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release_lock (&sysblk.intlock);
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}
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RETURN_INTCHECK(regs);
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}
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/*-------------------------------------------------------------------*/
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/* B238 RSCH - Resume Subchannel [S] */
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/*-------------------------------------------------------------------*/
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DEF_INST(resume_subchannel)
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{
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int b2; /* Effective addr base */
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VADR effective_addr2; /* Effective address */
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DEVBLK *dev; /* -> device block */
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S(inst, execflag, regs, b2, effective_addr2);
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PRIV_CHECK(regs);
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SIE_INTERCEPT(regs);
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/* Program check if reg 1 bits 0-15 not X'0001' */
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if ( regs->GR_LHH(1) != 0x0001 )
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ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
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/* Locate the device block for this subchannel */
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dev = find_device_by_subchan (regs->GR_LHL(1));
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/* Condition code 3 if subchannel does not exist,
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is not valid, or is not enabled */
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if (dev == NULL
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|| (dev->pmcw.flag5 & PMCW5_V) == 0
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|| (dev->pmcw.flag5 & PMCW5_E) == 0)
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{
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regs->psw.cc = 3;
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return;
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}
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/* Perform resume subchannel and set condition code */
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regs->psw.cc = resume_subchan (regs, dev);
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regs->siocount++;
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}
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/*-------------------------------------------------------------------*/
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/* B237 SAL - Set Address Limit [S] */
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/*-------------------------------------------------------------------*/
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DEF_INST(set_address_limit)
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{
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int b2; /* Effective addr base */
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VADR effective_addr2; /* Effective address */
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S(inst, execflag, regs, b2, effective_addr2);
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PRIV_CHECK(regs);
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SIE_INTERCEPT(regs);
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if(regs->GR_L(1) & 0x8000FFFF)
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ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
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else
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sysblk.addrlimval = regs->GR_L(1);
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}
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/*-------------------------------------------------------------------*/
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/* B23C SCHM - Set Channel Monitor [S] */
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/*-------------------------------------------------------------------*/
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DEF_INST(set_channel_monitor)
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{
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int b2; /* Effective addr base */
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VADR effective_addr2; /* Effective address */
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S(inst, execflag, regs, b2, effective_addr2);
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PRIV_CHECK(regs);
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SIE_INTERCEPT(regs);
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/* Reserved bits in gpr1 must be zero */
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if (regs->GR_L(1) & CHM_GPR1_RESV)
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ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
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/* Program check if M bit one and gpr2 address not on
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a 32 byte boundary or highorder bit set in ESA/390 mode */
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if ((regs->GR_L(1) & CHM_GPR1_M)
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&& (regs->GR_L(2) & CHM_GPR2_RESV))
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ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
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/* Set the measurement block origin address */
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if (regs->GR_L(1) & CHM_GPR1_M)
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{
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sysblk.mbo = regs->GR(2);
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sysblk.mbk = (regs->GR_L(1) & CHM_GPR1_MBK) >> 24;
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sysblk.mbm = 1;
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}
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else
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sysblk.mbm = 0;
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sysblk.mbd = regs->GR_L(1) & CHM_GPR1_D;
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}
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/*-------------------------------------------------------------------*/
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/* B233 SSCH - Start Subchannel [S] */
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/*-------------------------------------------------------------------*/
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DEF_INST(start_subchannel)
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{
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int b2; /* Effective addr base */
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VADR effective_addr2; /* Effective address */
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DEVBLK *dev; /* -> device block */
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ORB orb; /* Operation request block */
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S(inst, execflag, regs, b2, effective_addr2);
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PRIV_CHECK(regs);
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SIE_INTERCEPT(regs);
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FW_CHECK(effective_addr2, regs);
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/* Fetch the operation request block */
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ARCH_DEP(vfetchc) ( &orb, sizeof(ORB)-1, effective_addr2, b2, regs );
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/* Program check if reserved bits are not zero */
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if (orb.flag5 & ORB5_RESV
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|| orb.flag7 & ORB7_RESV
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|| orb.ccwaddr[0] & 0x80)
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ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
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#if !defined(FEATURE_INCORRECT_LENGTH_INDICATION_SUPPRESSION)
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/* Program check if incorrect length suppression */
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if (orb.flag7 & ORB7_L)
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ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
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#endif /*!defined(FEATURE_INCORRECT_LENGTH_INDICATION_SUPPRESSION)*/
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/* Program check if reg 1 bits 0-15 not X'0001' */
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if ( regs->GR_LHH(1) != 0x0001 )
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ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
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/* Locate the device block for this subchannel */
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dev = find_device_by_subchan (regs->GR_LHL(1));
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/* Condition code 3 if subchannel does not exist,
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is not valid, is not enabled, or no path available */
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if (dev == NULL
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|| (dev->pmcw.flag5 & PMCW5_V) == 0
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|| (dev->pmcw.flag5 & PMCW5_E) == 0
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|| (orb.lpm & dev->pmcw.pam) == 0)
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{
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regs->psw.cc = 3;
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return;
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}
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/* Perform serialization and checkpoint-synchronization */
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PERFORM_SERIALIZATION (regs);
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PERFORM_CHKPT_SYNC (regs);
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/* Clear the path not operational mask */
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dev->pmcw.pnom = 0;
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/* Copy the logical path mask */
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dev->pmcw.lpm = orb.lpm;
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/* Start the channel program and set the condition code */
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regs->psw.cc = ARCH_DEP(startio) (dev, &orb); /*@IWZ*/
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regs->siocount++;
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/* Set the last path used mask */
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if (0 == regs->psw.cc) dev->pmcw.lpum = 0x80;
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}
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/*-------------------------------------------------------------------*/
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/* B23A STCPS - Store Channel Path Status [S] */
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/*-------------------------------------------------------------------*/
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DEF_INST(store_channel_path_status)
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{
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int b2; /* Effective addr base */
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VADR effective_addr2; /* Effective address */
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BYTE work[32]; /* Work area */
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S(inst, execflag, regs, b2, effective_addr2);
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PRIV_CHECK(regs);
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SIE_INTERCEPT(regs);
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/* Program check if operand not on 32 byte boundary */
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if ( effective_addr2 & 0x0000001F )
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ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
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/*INCOMPLETE, SET TO ALL ZEROS*/
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memset(work,0x00,32);
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/* Store channel path status word at operand address */
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ARCH_DEP(vstorec) ( work, 32-1, effective_addr2, b2, regs );
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}
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/*-------------------------------------------------------------------*/
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/* B239 STCRW - Store Channel Report Word [S] */
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/*-------------------------------------------------------------------*/
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DEF_INST(store_channel_report_word)
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{
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int b2; /* Effective addr base */
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VADR effective_addr2; /* Effective address */
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U32 n; /* Integer work area */
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S(inst, execflag, regs, b2, effective_addr2);
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PRIV_CHECK(regs);
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SIE_INTERCEPT(regs);
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FW_CHECK(effective_addr2, regs);
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/* Validate write access to operand before taking any
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pending channel report word off the queue */
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ARCH_DEP(validate_operand) (effective_addr2, b2, 0, ACCTYPE_WRITE, regs);
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/* Obtain any pending channel report */
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n = channel_report();
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/* Store channel report word at operand address */
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ARCH_DEP(vstore4) ( n, effective_addr2, b2, regs );
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/* Indicate if channel report or zeros were stored */
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regs->psw.cc = (n == 0) ? 1 : 0;
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}
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/*-------------------------------------------------------------------*/
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/* B234 STSCH - Store Subchannel [S] */
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/*-------------------------------------------------------------------*/
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DEF_INST(store_subchannel)
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{
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int b2; /* Effective addr base */
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VADR effective_addr2; /* Effective address */
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DEVBLK *dev; /* -> device block */
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SCHIB schib; /* Subchannel information blk*/
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S(inst, execflag, regs, b2, effective_addr2);
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PRIV_CHECK(regs);
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SIE_INTERCEPT(regs);
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/* Program check if reg 1 bits 0-15 not X'0001' */
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if ( regs->GR_LHH(1) != 0x0001 )
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ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
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|
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/* Locate the device block for this subchannel */
|
|
dev = find_device_by_subchan (regs->GR_LHL(1));
|
|
|
|
/* Set condition code 3 if subchannel does not exist */
|
|
if (dev == NULL)
|
|
{
|
|
regs->psw.cc = 3;
|
|
return;
|
|
}
|
|
|
|
FW_CHECK(effective_addr2, regs);
|
|
|
|
/* Perform serialization and checkpoint-synchronization */
|
|
PERFORM_SERIALIZATION (regs);
|
|
PERFORM_CHKPT_SYNC (regs);
|
|
|
|
/* Build the subchannel information block */
|
|
schib.pmcw = dev->pmcw;
|
|
schib.scsw = dev->scsw;
|
|
memset (schib.moddep, 0, sizeof(schib.moddep));
|
|
|
|
/* Store the subchannel information block */
|
|
ARCH_DEP(vstorec) ( &schib, sizeof(SCHIB)-1, effective_addr2,
|
|
b2, regs );
|
|
|
|
/* Set condition code 0 */
|
|
regs->psw.cc = 0;
|
|
|
|
}
|
|
|
|
|
|
/*-------------------------------------------------------------------*/
|
|
/* B236 TPI - Test Pending Interruption [S] */
|
|
/*-------------------------------------------------------------------*/
|
|
DEF_INST(test_pending_interruption)
|
|
{
|
|
int b2; /* Effective addr base */
|
|
VADR effective_addr2; /* Effective address */
|
|
PSA *psa; /* -> Prefixed storage area */
|
|
U64 dreg; /* Double register work area */
|
|
U32 ioid; /* I/O interruption address */
|
|
U32 ioparm; /* I/O interruption parameter*/
|
|
U32 iointid; /* I/O interruption ident */
|
|
|
|
S(inst, execflag, regs, b2, effective_addr2);
|
|
|
|
PRIV_CHECK(regs);
|
|
|
|
SIE_INTERCEPT(regs);
|
|
|
|
FW_CHECK(effective_addr2, regs);
|
|
|
|
/* validate operand before taking any action */
|
|
if ( effective_addr2 != 0 )
|
|
ARCH_DEP(validate_operand) (effective_addr2, b2, 8-1,
|
|
ACCTYPE_WRITE, regs);
|
|
|
|
/* Perform serialization and checkpoint-synchronization */
|
|
PERFORM_SERIALIZATION (regs);
|
|
PERFORM_CHKPT_SYNC (regs);
|
|
|
|
if( IS_IC_IOPENDING )
|
|
{
|
|
/* Obtain the interrupt lock */
|
|
obtain_lock (&sysblk.intlock);
|
|
|
|
/* Test and clear pending interrupt, set condition code */
|
|
regs->psw.cc =
|
|
ARCH_DEP(present_io_interrupt) (regs, &ioid, &ioparm,
|
|
&iointid, NULL);
|
|
|
|
/* Release the interrupt lock */
|
|
release_lock (&sysblk.intlock);
|
|
|
|
/* Store the SSID word and I/O parameter if an interrupt was pending */
|
|
if (regs->psw.cc)
|
|
{
|
|
if ( effective_addr2 == 0 )
|
|
{
|
|
/* If operand address is zero, store in PSA */
|
|
psa = (void*)(sysblk.mainstor + regs->PX);
|
|
STORE_FW(psa->ioid,ioid);
|
|
STORE_FW(psa->ioparm,ioparm);
|
|
#if defined(FEATURE_ESAME)
|
|
STORE_FW(psa->iointid,iointid);
|
|
#endif /*defined(FEATURE_ESAME)*/
|
|
STORAGE_KEY(regs->PX) |= (STORKEY_REF|STORKEY_CHANGE);
|
|
}
|
|
else
|
|
{
|
|
/* Otherwise store at operand location */
|
|
dreg = ((U64)ioid << 32) | ioparm;
|
|
ARCH_DEP(vstore8) ( dreg, effective_addr2, b2, regs );
|
|
}
|
|
}
|
|
}
|
|
else
|
|
regs->psw.cc = 0;
|
|
|
|
}
|
|
|
|
|
|
/*-------------------------------------------------------------------*/
|
|
/* B235 TSCH - Test Subchannel [S] */
|
|
/*-------------------------------------------------------------------*/
|
|
DEF_INST(test_subchannel)
|
|
{
|
|
int b2; /* Effective addr base */
|
|
VADR effective_addr2; /* Effective address */
|
|
DEVBLK *dev; /* -> device block */
|
|
IRB irb; /* Interruption response blk */
|
|
|
|
S(inst, execflag, regs, b2, effective_addr2);
|
|
|
|
PRIV_CHECK(regs);
|
|
|
|
SIE_INTERCEPT(regs);
|
|
|
|
FW_CHECK(effective_addr2, regs);
|
|
|
|
/* Program check if reg 1 bits 0-15 not X'0001' */
|
|
if ( regs->GR_LHH(1) != 0x0001 )
|
|
ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
|
|
|
|
/* Locate the device block for this subchannel */
|
|
dev = find_device_by_subchan (regs->GR_LHL(1));
|
|
|
|
/* Condition code 3 if subchannel does not exist,
|
|
is not valid, or is not enabled */
|
|
if (dev == NULL
|
|
|| (dev->pmcw.flag5 & PMCW5_V) == 0
|
|
|| (dev->pmcw.flag5 & PMCW5_E) == 0)
|
|
{
|
|
regs->psw.cc = 3;
|
|
return;
|
|
}
|
|
|
|
/* validate operand before taking any action */
|
|
ARCH_DEP(validate_operand) (effective_addr2, b2, sizeof(IRB)-1,
|
|
ACCTYPE_WRITE, regs);
|
|
|
|
/* Perform serialization and checkpoint-synchronization */
|
|
PERFORM_SERIALIZATION (regs);
|
|
PERFORM_CHKPT_SYNC (regs);
|
|
|
|
/* Test and clear pending status, set condition code */
|
|
regs->psw.cc = test_subchan (regs, dev, &irb);
|
|
|
|
/* Store the interruption response block */
|
|
ARCH_DEP(vstorec) ( &irb, sizeof(IRB)-1, effective_addr2, b2, regs );
|
|
|
|
}
|
|
|
|
|
|
#if defined(FEATURE_CANCEL_IO_FACILITY)
|
|
/*-------------------------------------------------------------------*/
|
|
/* B276 XSCH - Cancel Subchannel [S] */
|
|
/*-------------------------------------------------------------------*/
|
|
DEF_INST(cancel_subchannel)
|
|
{
|
|
int b2; /* Base of effective addr */
|
|
VADR effective_addr2; /* Effective address */
|
|
DEVBLK *dev; /* -> device block */
|
|
|
|
S(inst, execflag, regs, b2, effective_addr2);
|
|
|
|
PRIV_CHECK(regs);
|
|
|
|
SIE_INTERCEPT(regs);
|
|
|
|
/* Program check if reg 1 bits 0-15 not X'0001' */
|
|
if ( regs->GR_LHH(1) != 0x0001 )
|
|
ARCH_DEP(program_interrupt) (regs, PGM_OPERAND_EXCEPTION);
|
|
|
|
/* Locate the device block for this subchannel */
|
|
dev = find_device_by_subchan (regs->GR_LHL(1));
|
|
|
|
/* Condition code 3 if subchannel does not exist,
|
|
is not valid, or is not enabled */
|
|
if (dev == NULL
|
|
|| (dev->pmcw.flag5 & PMCW5_V) == 0
|
|
|| (dev->pmcw.flag5 & PMCW5_E) == 0)
|
|
{
|
|
regs->psw.cc = 3;
|
|
return;
|
|
}
|
|
|
|
/* Perform cancel subchannel and set condition code */
|
|
regs->psw.cc = cancel_subchan (regs, dev);
|
|
|
|
}
|
|
#endif /*defined(FEATURE_CANCEL_IO_FACILITY)*/
|
|
#endif /*defined(FEATURE_CHANNEL_SUBSYSTEM)*/
|
|
|
|
|
|
#if defined(FEATURE_S370_CHANNEL)
|
|
|
|
/*-------------------------------------------------------------------*/
|
|
/* 9C00 SIO - Start I/O [S] */
|
|
/* 9C01 SIOF - Start I/O Fast Release [S] */
|
|
/* 9C02 RIO - Resume I/O - ZZ INCOMPLETE [S] */
|
|
/*-------------------------------------------------------------------*/
|
|
DEF_INST(start_io)
|
|
{
|
|
int b2; /* Effective addr base */
|
|
VADR effective_addr2; /* Effective address */
|
|
PSA *psa; /* -> prefixed storage area */
|
|
DEVBLK *dev; /* -> device block for SIO */
|
|
ORB orb; /* Operation request blk @IZW*/
|
|
VADR ccwaddr; /* CCW address for start I/O */
|
|
BYTE ccwkey; /* Bits 0-3=key, 4=7=zeroes */
|
|
|
|
S(inst, execflag, regs, b2, effective_addr2);
|
|
|
|
PRIV_CHECK(regs);
|
|
|
|
SIE_INTERCEPT(regs);
|
|
|
|
/* Locate the device block */
|
|
dev = find_device_by_devnum (effective_addr2);
|
|
|
|
/* Set condition code 3 if device does not exist */
|
|
if (dev == NULL
|
|
#if defined(FEATURE_CHANNEL_SWITCHING)
|
|
|| regs->chanset != dev->chanset
|
|
#endif /*defined(FEATURE_CHANNEL_SWITCHING)*/
|
|
)
|
|
{
|
|
regs->psw.cc = 3;
|
|
return;
|
|
}
|
|
|
|
/* Fetch key and CCW address from the CAW at PSA+X'48' */
|
|
psa = (PSA*)(sysblk.mainstor + regs->PX);
|
|
ccwkey = psa->caw[0] & 0xF0;
|
|
ccwaddr = (psa->caw[1] << 16) | (psa->caw[2] << 8)
|
|
| psa->caw[3];
|
|
|
|
/* Build the I/O operation request block */ /*@IZW*/
|
|
memset (&orb, 0, sizeof(ORB)); /*@IZW*/
|
|
orb.flag4 = ccwkey & ORB4_KEY; /*@IZW*/
|
|
STORE_FW(orb.ccwaddr,ccwaddr); /*@IZW*/
|
|
|
|
/* Start the channel program and set the condition code */
|
|
regs->psw.cc = ARCH_DEP(startio) (dev, &orb); /*@IZW*/
|
|
|
|
regs->siocount++;
|
|
|
|
}
|
|
|
|
|
|
/*-------------------------------------------------------------------*/
|
|
/* 9D00 TIO - Test I/O [S] */
|
|
/* 9D01 CLRIO - Clear I/O [S] */
|
|
/*-------------------------------------------------------------------*/
|
|
DEF_INST(test_io)
|
|
{
|
|
int b2; /* Base of effective addr */
|
|
VADR effective_addr2; /* Effective address */
|
|
DEVBLK *dev; /* -> device block for SIO */
|
|
|
|
S(inst, execflag, regs, b2, effective_addr2);
|
|
|
|
PRIV_CHECK(regs);
|
|
|
|
SIE_INTERCEPT(regs);
|
|
|
|
/* Locate the device block */
|
|
dev = find_device_by_devnum (effective_addr2);
|
|
|
|
/* Set condition code 3 if device does not exist */
|
|
if (dev == NULL
|
|
#if defined(FEATURE_CHANNEL_SWITCHING)
|
|
|| regs->chanset != dev->chanset
|
|
#endif /*defined(FEATURE_CHANNEL_SWITCHING)*/
|
|
)
|
|
{
|
|
regs->psw.cc = 3;
|
|
return;
|
|
}
|
|
|
|
/* Test the device and set the condition code */
|
|
regs->psw.cc = testio (regs, dev, inst[1]);
|
|
|
|
}
|
|
|
|
|
|
/*-------------------------------------------------------------------*/
|
|
/* 9E00 HIO - Halt I/O [S] */
|
|
/* 9E01 HDV - Halt Device [S] */
|
|
/*-------------------------------------------------------------------*/
|
|
DEF_INST(halt_io)
|
|
{
|
|
int b2; /* Base of effective addr */
|
|
VADR effective_addr2; /* Effective address */
|
|
DEVBLK *dev; /* -> device block for SIO */
|
|
|
|
S(inst, execflag, regs, b2, effective_addr2);
|
|
|
|
PRIV_CHECK(regs);
|
|
|
|
SIE_INTERCEPT(regs);
|
|
|
|
/* Locate the device block */
|
|
dev = find_device_by_devnum (effective_addr2);
|
|
|
|
/* Set condition code 3 if device does not exist */
|
|
if (dev == NULL
|
|
#if defined(FEATURE_CHANNEL_SWITCHING)
|
|
|| regs->chanset != dev->chanset
|
|
#endif /*defined(FEATURE_CHANNEL_SWITCHING)*/
|
|
)
|
|
{
|
|
regs->psw.cc = 3;
|
|
return;
|
|
}
|
|
|
|
/* Test the device and set the condition code */
|
|
regs->psw.cc = haltio (regs, dev, inst[1]);
|
|
|
|
}
|
|
|
|
|
|
/*-------------------------------------------------------------------*/
|
|
/* 9F00 TCH - Test Channel [S] */
|
|
/*-------------------------------------------------------------------*/
|
|
DEF_INST(test_channel)
|
|
{
|
|
int b2; /* Base of effective addr */
|
|
VADR effective_addr2; /* Effective address */
|
|
#if defined(_FEATURE_SIE)
|
|
BYTE channelid;
|
|
U16 tch_ctl;
|
|
#endif /*defined(_FEATURE_SIE)*/
|
|
|
|
S(inst, execflag, regs, b2, effective_addr2);
|
|
|
|
PRIV_CHECK(regs);
|
|
|
|
#if defined(_FEATURE_SIE)
|
|
if(!regs->sie_state)
|
|
{
|
|
#endif /*defined(_FEATURE_SIE)*/
|
|
/* Test for pending interrupt and set condition code */
|
|
regs->psw.cc = testch (regs, effective_addr2 & 0xFF00);
|
|
#if defined(_FEATURE_SIE)
|
|
}
|
|
else
|
|
{
|
|
channelid = (effective_addr2 >> 8) & 0xFF;
|
|
FETCH_HW(tch_ctl,((SIEBK*)(regs->siebk))->tch_ctl);
|
|
if((channelid > 15)
|
|
|| ((0x8000 >> channelid) & tch_ctl))
|
|
longjmp(regs->progjmp, SIE_INTERCEPT_INST);
|
|
else
|
|
regs->psw.cc = 0;
|
|
}
|
|
#endif /*defined(_FEATURE_SIE)*/
|
|
|
|
}
|
|
|
|
|
|
/*-------------------------------------------------------------------*/
|
|
/* B203 STIDC - Store Channel ID [S] */
|
|
/*-------------------------------------------------------------------*/
|
|
DEF_INST(store_channel_id)
|
|
{
|
|
int b2; /* Base of effective addr */
|
|
VADR effective_addr2; /* Effective address */
|
|
|
|
S(inst, execflag, regs, b2, effective_addr2);
|
|
|
|
PRIV_CHECK(regs);
|
|
|
|
SIE_INTERCEPT(regs);
|
|
|
|
/* Store Channel ID and set condition code */
|
|
regs->psw.cc =
|
|
stchan_id (regs, effective_addr2 & 0xFF00);
|
|
|
|
}
|
|
|
|
|
|
#if defined(FEATURE_CHANNEL_SWITCHING)
|
|
/*-------------------------------------------------------------------*/
|
|
/* B200 CONCS - Connect Channel Set [S] */
|
|
/*-------------------------------------------------------------------*/
|
|
DEF_INST(connect_channel_set)
|
|
{
|
|
int b2; /* Base of effective addr */
|
|
VADR effective_addr2; /* Effective address */
|
|
int i;
|
|
|
|
S(inst, execflag, regs, b2, effective_addr2);
|
|
|
|
// ZZTEMP ARCH_DEP(display_inst) (regs, inst);
|
|
|
|
PRIV_CHECK(regs);
|
|
|
|
SIE_INTERCEPT(regs);
|
|
|
|
effective_addr2 &= 0xFFFF;
|
|
|
|
/* Hercules has as many channelsets as CPU's */
|
|
if(effective_addr2 >= MAX_CPU_ENGINES)
|
|
{
|
|
regs->psw.cc = 3;
|
|
return;
|
|
}
|
|
|
|
/* If the addressed channel set is currently connected
|
|
then return with cc0 */
|
|
if(regs->chanset == effective_addr2)
|
|
{
|
|
regs->psw.cc = 0;
|
|
return;
|
|
}
|
|
|
|
/* Disconnect channel set */
|
|
regs->chanset = 0xFFFF;
|
|
|
|
obtain_lock(&sysblk.intlock);
|
|
|
|
/* If the addressed channelset is connected to another
|
|
CPU then return with cc1 */
|
|
for(i = 0; i < MAX_CPU_ENGINES; i++)
|
|
{
|
|
if(sysblk.regs[i].chanset == effective_addr2)
|
|
{
|
|
release_lock(&sysblk.intlock);
|
|
regs->psw.cc = 1;
|
|
return;
|
|
}
|
|
}
|
|
|
|
/* Set channel set connected to current CPU */
|
|
regs->chanset = effective_addr2;
|
|
|
|
/* Interrupts may be pending on this channelset */
|
|
ON_IC_IOPENDING;
|
|
|
|
release_lock(&sysblk.intlock);
|
|
|
|
regs->psw.cc = 0;
|
|
|
|
}
|
|
|
|
|
|
/*-------------------------------------------------------------------*/
|
|
/* B201 DISCS - Disconnect Channel Set [S] */
|
|
/*-------------------------------------------------------------------*/
|
|
DEF_INST(disconnect_channel_set)
|
|
{
|
|
int b2; /* Base of effective addr */
|
|
VADR effective_addr2; /* Effective address */
|
|
int i;
|
|
|
|
S(inst, execflag, regs, b2, effective_addr2);
|
|
|
|
// ZZTEMP ARCH_DEP(display_inst) (regs, inst);
|
|
|
|
PRIV_CHECK(regs);
|
|
|
|
SIE_INTERCEPT(regs);
|
|
|
|
/* Hercules has as many channelsets as CPU's */
|
|
if(effective_addr2 >= MAX_CPU_ENGINES)
|
|
{
|
|
regs->psw.cc = 3;
|
|
return;
|
|
}
|
|
|
|
/* If the addressed channel set is currently connected
|
|
then disconect channel set and return with cc0 */
|
|
if(regs->chanset == effective_addr2 && regs->chanset != 0xFFFF)
|
|
{
|
|
regs->chanset = 0xFFFF;
|
|
regs->psw.cc = 0;
|
|
return;
|
|
}
|
|
|
|
obtain_lock(&sysblk.intlock);
|
|
|
|
/* If the addressed channelset is connected to another
|
|
CPU then return with cc0 */
|
|
for(i = 0; i < MAX_CPU_ENGINES; i++)
|
|
{
|
|
if(sysblk.regs[i].chanset == effective_addr2)
|
|
{
|
|
if(sysblk.regs[i].cpustate != CPUSTATE_STARTED)
|
|
{
|
|
sysblk.regs[i].chanset = 0xFFFF;
|
|
regs->psw.cc = 0;
|
|
}
|
|
else
|
|
regs->psw.cc = 1;
|
|
release_lock(&sysblk.intlock);
|
|
return;
|
|
}
|
|
}
|
|
|
|
release_lock(&sysblk.intlock);
|
|
|
|
/* The channel set is not connected, no operation
|
|
is performed */
|
|
regs->psw.cc = 0;
|
|
|
|
}
|
|
#endif /*defined(FEATURE_CHANNEL_SWITCHING)*/
|
|
|
|
#endif /*defined(FEATURE_S370_CHANNEL)*/
|
|
|
|
|
|
#if !defined(_GEN_ARCH)
|
|
|
|
#if defined(_ARCHMODE2)
|
|
#define _GEN_ARCH _ARCHMODE2
|
|
#include "io.c"
|
|
#endif
|
|
|
|
#if defined(_ARCHMODE3)
|
|
#undef _GEN_ARCH
|
|
#define _GEN_ARCH _ARCHMODE3
|
|
#include "io.c"
|
|
#endif
|
|
|
|
#endif /*!defined(_GEN_ARCH)*/
|