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Decimal Floating Point: SLXT,SLDT,SRDT instructions
git-svn-id: file:///home/jj/hercules.svn/trunk@4261 956126f8-22a0-4046-8f4a-272fa8102e63
This commit is contained in:
Roger Bowler
184
dfp.c
184
dfp.c
@@ -10,6 +10,9 @@
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/*-------------------------------------------------------------------*/
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// $Log$
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// Revision 1.47 2007/01/20 22:22:42 rbowler
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// Decimal Floating Point: SRXT instruction (part 2)
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//
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// Revision 1.46 2007/01/19 15:46:33 rbowler
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// Decimal Floating Point: SRXT instruction (part 1)
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//
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@@ -2654,8 +2657,125 @@ BYTE dxc; /* Data exception code */
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} /* end DEF_INST(set_fpc_and_signal) */
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UNDEF_INST(shift_coefficient_left_dfp_ext)
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UNDEF_INST(shift_coefficient_left_dfp_long)
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/*-------------------------------------------------------------------*/
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/* ED48 SLXT - Shift Coefficient Left DFP Extended [RXF] */
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/*-------------------------------------------------------------------*/
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DEF_INST(shift_coefficient_left_dfp_ext)
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{
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int r1, r3; /* Values of R fields */
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int b2; /* Base of effective addr */
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VADR effective_addr2; /* Effective address */
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decimal128 x1, x3; /* Extended DFP values */
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decNumber d1, d3; /* Working decimal numbers */
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decContext set; /* Working context */
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int n; /* Number of bits to shift */
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RXF(inst, regs, r1, r3, b2, effective_addr2);
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DFPINST_CHECK(regs);
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DFPREGPAIR2_CHECK(r1, r3, regs);
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/* Isolate rightmost 6 bits of second operand address */
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n = effective_addr2 & 0x3F;
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/* Initialise the context for extended DFP */
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decContextDefault(&set, DEC_INIT_DECIMAL128);
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/* Load DFP extended number from FP register r3 */
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ARCH_DEP(dfp_reg_to_decimal128)(r3, &x3, regs);
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/* Convert to internal decimal number format */
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decimal128ToNumber(&x3, &d3);
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/* For NaN and Inf use coefficient continuation digits only */
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if (decNumberIsNaN(&d3) || decNumberIsInfinite(&d3))
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{
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dfp128_clear_cf_and_bxcf(&x3);
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decimal128ToNumber(&x3, &d1);
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}
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else
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{
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decNumberCopy(&d1, &d3);
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}
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/* Shift coefficient left n digit positions */
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dfp_shift_coeff(&set, &d1, n);
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/* Convert result to DFP extended format */
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decimal128FromNumber(&x1, &d1, &set);
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/* Restore Nan or Inf indicators in the result */
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if (decNumberIsQNaN(&d3))
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dfp128_set_cf_and_bxcf(&x1, DFP_CFS_QNAN);
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else if (decNumberIsSNaN(&d3))
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dfp128_set_cf_and_bxcf(&x1, DFP_CFS_SNAN);
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else if (decNumberIsInfinite(&d3))
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dfp128_set_cf_and_bxcf(&x1, DFP_CFS_INF);
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/* Load result into FP register r1 */
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ARCH_DEP(dfp_reg_from_decimal128)(r1, &x1, regs);
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} /* end DEF_INST(shift_coefficient_left_dfp_ext) */
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/*-------------------------------------------------------------------*/
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/* ED40 SLDT - Shift Coefficient Left DFP Long [RXF] */
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/*-------------------------------------------------------------------*/
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DEF_INST(shift_coefficient_left_dfp_long)
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{
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int r1, r3; /* Values of R fields */
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int b2; /* Base of effective addr */
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VADR effective_addr2; /* Effective address */
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decimal64 x1, x3; /* Long DFP values */
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decNumber d1, d3; /* Working decimal numbers */
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decContext set; /* Working context */
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int n; /* Number of bits to shift */
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RXF(inst, regs, r1, r3, b2, effective_addr2);
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DFPINST_CHECK(regs);
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/* Isolate rightmost 6 bits of second operand address */
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n = effective_addr2 & 0x3F;
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/* Initialise the context for long DFP */
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decContextDefault(&set, DEC_INIT_DECIMAL64);
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/* Load DFP long number from FP register r3 */
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ARCH_DEP(dfp_reg_to_decimal64)(r3, &x3, regs);
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/* Convert to internal decimal number format */
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decimal64ToNumber(&x3, &d3);
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/* For NaN and Inf use coefficient continuation digits only */
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if (decNumberIsNaN(&d3) || decNumberIsInfinite(&d3))
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{
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dfp64_clear_cf_and_bxcf(&x3);
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decimal64ToNumber(&x3, &d1);
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}
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else
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{
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decNumberCopy(&d1, &d3);
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}
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/* Shift coefficient left n digit positions */
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dfp_shift_coeff(&set, &d1, n);
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/* Convert result to DFP long format */
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decimal64FromNumber(&x1, &d1, &set);
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/* Restore Nan or Inf indicators in the result */
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if (decNumberIsQNaN(&d3))
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dfp64_set_cf_and_bxcf(&x1, DFP_CFS_QNAN);
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else if (decNumberIsSNaN(&d3))
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dfp64_set_cf_and_bxcf(&x1, DFP_CFS_SNAN);
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else if (decNumberIsInfinite(&d3))
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dfp64_set_cf_and_bxcf(&x1, DFP_CFS_INF);
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/* Load result into FP register r1 */
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ARCH_DEP(dfp_reg_from_decimal64)(r1, &x1, regs);
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} /* end DEF_INST(shift_coefficient_left_dfp_long) */
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/*-------------------------------------------------------------------*/
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/* ED49 SRXT - Shift Coefficient Right DFP Extended [RXF] */
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/*-------------------------------------------------------------------*/
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@@ -2716,7 +2836,65 @@ int n; /* Number of bits to shift */
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} /* end DEF_INST(shift_coefficient_right_dfp_ext) */
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UNDEF_INST(shift_coefficient_right_dfp_long)
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/*-------------------------------------------------------------------*/
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/* ED41 SRDT - Shift Coefficient Right DFP Long [RXF] */
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/*-------------------------------------------------------------------*/
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DEF_INST(shift_coefficient_right_dfp_long)
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{
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int r1, r3; /* Values of R fields */
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int b2; /* Base of effective addr */
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VADR effective_addr2; /* Effective address */
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decimal64 x1, x3; /* Long DFP values */
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decNumber d1, d3; /* Working decimal numbers */
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decContext set; /* Working context */
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int n; /* Number of bits to shift */
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RXF(inst, regs, r1, r3, b2, effective_addr2);
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DFPINST_CHECK(regs);
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/* Isolate rightmost 6 bits of second operand address */
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n = effective_addr2 & 0x3F;
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/* Initialise the context for long DFP */
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decContextDefault(&set, DEC_INIT_DECIMAL64);
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/* Load DFP long number from FP register r3 */
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ARCH_DEP(dfp_reg_to_decimal64)(r3, &x3, regs);
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/* Convert to internal decimal number format */
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decimal64ToNumber(&x3, &d3);
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/* For NaN and Inf use coefficient continuation digits only */
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if (decNumberIsNaN(&d3) || decNumberIsInfinite(&d3))
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{
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dfp64_clear_cf_and_bxcf(&x3);
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decimal64ToNumber(&x3, &d1);
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}
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else
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{
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decNumberCopy(&d1, &d3);
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}
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/* Shift coefficient right n digit positions */
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dfp_shift_coeff(&set, &d1, -n);
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/* Convert result to DFP long format */
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decimal64FromNumber(&x1, &d1, &set);
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/* Restore Nan or Inf indicators in the result */
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if (decNumberIsQNaN(&d3))
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dfp64_set_cf_and_bxcf(&x1, DFP_CFS_QNAN);
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else if (decNumberIsSNaN(&d3))
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dfp64_set_cf_and_bxcf(&x1, DFP_CFS_SNAN);
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else if (decNumberIsInfinite(&d3))
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dfp64_set_cf_and_bxcf(&x1, DFP_CFS_INF);
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/* Load result into FP register r1 */
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ARCH_DEP(dfp_reg_from_decimal64)(r1, &x1, regs);
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} /* end DEF_INST(shift_coefficient_right_dfp_long) */
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/*-------------------------------------------------------------------*/
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/* B3DB SXTR - Subtract DFP Extended Register [RRR] */
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/*-------------------------------------------------------------------*/
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50
tests/srdt.txt
Normal file
50
tests/srdt.txt
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@@ -0,0 +1,50 @@
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* SRDT test $Id$
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sysclear
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archmode esame
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r 1a0=00000001800000000000000000000200 # z/Arch restart PSW
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r 1d0=0002000180000000000000000000DEAD # z/Arch pgm new PSW
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r 200=B7000310 # LCTL R0,R0,CTLR0 Set CR0 bit 45
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r 204=41000006 # LA R0,6 R0=Number of test data
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r 208=41100380 # LA R1,TEST1 R1=>Test data table
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r 20C=41F00400 # LA R15,RES1 R15=>Result table
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r 210=68601000 #A LD F6,0(,R1) Load FPR6=TESTn
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r 214=41200004 # LA R2,4 R2=Number of shift tests
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r 218=41300318 # LA R3,N1 R3=>Shift count table
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r 21C=58403000 #B L R4,0(,R3) Load R4=Nn
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r 220=ED6040008040 # SLDT F8,F6,0 Shift FPR6 left Nn digits
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r 226=6080F000 # STD F8,0(,R15) Store F8 in result table
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r 22A=41F0F008 # LA R15,8(,R15) R15=>next result table
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r 22E=B3E301E8 # CSDTR R14,F8,1 Convert to PACKED R14 from FPR8
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r 232=E3E0F0000024 # STG R14,0(,R15) Store R14 in result table
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r 238=41F0F008 # LA R15,8(,R15) R15=>next result table
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r 23C=ED6040008041 # SRDT F8,F6,0 Shift FPR6 right Nn digits
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r 242=6080F000 # STD F8,0(,R15) Store F8 in result table
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r 246=41F0F008 # LA R15,8(,R15) R15=>next result table
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r 24A=B3E301E8 # CSDTR R14,F8,1 Convert to PACKED R14 from FPR8
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r 24E=E3E0F0000024 # STG R14,0(,R15) Store R14 in result table
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r 254=41F0F008 # LA R15,8(,R15) R15=>next result table
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r 258=41303004 # LA R3,4(,R3) R3=>Next Nn
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r 25C=4620021C # BCT R2,B Loop to end of Nn table
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r 260=41101008 # LA R1,8(,R1) R1=>Next TESTn
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r 264=46000210 # BCT R0,A Loop to end of TESTn table
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r 268=B2B20300 # LPSWE WAITPSW Load enabled wait PSW
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r 300=07020001800000000000000000FED0D0 # WAITPSW Enabled wait state PSW
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r 310=00040000 # CTLR0 Control register 0 (bit45 AFP control)
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r 314=00000000 # FPCREG Floating point control register
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r 318=00000000 # N1 DC F'0' Shift count 0
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r 31C=FFFFFFC1 # N2 DC F'1' Shift count 1
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r 320=000002C4 # N3 DC F'708' Shift count 4
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r 324=0000003F # N4 DC F'63' Shift count 63
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r 380=2238000000000000 # TEST1 DC DD'0' Zero positive
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r 388=2238000012045078 # TEST2 DC DD'12045078' Normal positive
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r 390=ABCDEF0123456789 # TEST3 DC DD'2.989004434259709E116' Large positive
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r 398=7CABCDEF01234567 # TEST4 DC DD'QNAN' QNaN positive
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r 3A0=FE0000000000ABCD # TEST5 DC DD'-SNAN' SNaN negative
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r 3A8=78123456789ABCDE # TEST6 DC DD'INF' Infinity positive
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restart
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pause 1
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* Display test data
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r 318.10
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r 380.30
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* Display results
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r 400.300
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