mirror of
https://github.com/SDL-Hercules-390/hyperion.git
synced 2026-08-14 05:42:59 +02:00
Additional I/O interrupt cleanup; only wakeup a waiting CPU if enabled for I/O interrupts.
This commit is contained in:
dasdman
@@ -322,7 +322,11 @@ scsw_clear_ac_Nr (SCSW* scsw)
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static INLINE void
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scsw_clear_sc_Cs (SCSW* scsw)
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{
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scsw->flag3 &= ~SCSW3_SC_PEND;
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scsw->flag3 &= ~(SCSW3_SC_ALERT |
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SCSW3_SC_INTER |
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SCSW3_SC_PRI |
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SCSW3_SC_SEC |
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SCSW3_SC_PEND);
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}
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@@ -3775,13 +3779,13 @@ int rc; /* Return code */
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/* Initialize the subchannel status word */
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memset (&dev->scsw, 0, sizeof(SCSW));
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dev->scsw.flag0 = (orb->flag4 & SCSW0_KEY); /*@IWZ*/
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if (orb->flag4 & ORB4_S) dev->scsw.flag0 |= SCSW0_S; /*@IWZ*/
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if (orb->flag5 & ORB5_F) dev->scsw.flag1 |= SCSW1_F; /*@IWZ*/
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if (orb->flag5 & ORB5_P) dev->scsw.flag1 |= SCSW1_P; /*@IWZ*/
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if (orb->flag5 & ORB5_I) dev->scsw.flag1 |= SCSW1_I; /*@IWZ*/
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if (orb->flag5 & ORB5_A) dev->scsw.flag1 |= SCSW1_A; /*@IWZ*/
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if (orb->flag5 & ORB5_U) dev->scsw.flag1 |= SCSW1_U; /*@IWZ*/
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dev->scsw.flag0 = (orb->flag4 & (SCSW0_KEY |
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SCSW0_S));
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dev->scsw.flag1 = (orb->flag5 & (SCSW1_F |
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SCSW1_P |
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SCSW1_I |
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SCSW1_A |
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SCSW1_U));
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/* Set the device busy indicator */
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set_subchannel_busy(dev);
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@@ -5538,7 +5542,38 @@ retry:
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}
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/* See if another CPU can take this interrupt */
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WAKEUP_CPU_MASK (sysblk.waiting_mask);
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{
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REGS *regs;
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CPU_BITMAP mask = sysblk.waiting_mask;
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CPU_BITMAP wake;
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int i;
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/* If any CPUs are waiting, isolate to subgroup enabled for
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* I/O interrupts.
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*/
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if (mask)
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{
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wake = mask;
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/* Turn off wake mask bits for waiting CPUs that aren't
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* enabled for I/O interrupts.
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*/
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for (i = 0; mask; mask >>= 1, ++i)
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{
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if (mask & 1)
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{
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regs = sysblk.regs[i];
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if (!OPEN_IC_IOPENDING(regs))
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wake ^= regs->cpubit;
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}
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}
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/* Wakeup the LRU waiting CPU enabled for I/O
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* interrupts.
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*/
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WAKEUP_CPU_MASK(wake);
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}
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}
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} /* end for(io) */
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@@ -5,7 +5,7 @@
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Interrupts_State & Interrupts_Mask bits definition (Initial_Mask=800E)
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Machine check, PER and external interrupt subclass bit positions
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are fixed by the architecture and cannot be changed
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Floating interrupts are made pending to all CPUs, and are
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Floating interrupts are made pending to all CPUs, and are
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recorded in the sysblk structure, CPU specific interrupts
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are recorded in the regs structure.
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hi0m mmmm pppp p00p xxxx xxxx xxxx h0hs : type U32
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@@ -25,22 +25,22 @@
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|| | |||| |||| | | |||| ||+-------------> '1' : SERVSIG
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|| | |||| |||| | | |||| |+--------------> '1' : PTIMER
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|| | |||| |||| | | |||| +---------------> '1' : CLKC
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|| | |||| |||| | | ||||
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|| | |||| |||| | | ||||
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|| | |||| |||| | | |||+-----------------> '1' : TODSYNC
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|| | |||| |||| | | ||+------------------> '1' : EXTCALL
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|| | |||| |||| | | |+-------------------> '1' : EMERSIG
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|| | |||| |||| | | +--------------------> '1' : MALFALT
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|| | |||| |||| | |
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|| | |||| |||| | +----------------------> '1' : PER IFNUL
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|| | |||| |||| |
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|| | |||| |||| |
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|| | |||| |||| |
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|| | |||| |||| |
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|| | |||| |||| +-------------------------> '1' : PER STURA
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|| | |||| ||||
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|| | |||| ||||
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|| | |||| |||+---------------------------> '1' : PER GRA
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|| | |||| ||+----------------------------> '1' : PER SA
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|| | |||| |+-----------------------------> '1' : PER IF
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|| | |||| +------------------------------> '1' : PER SB
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|| | ||||
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|| | ||||
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|| | |||+--------------------------------> '1' : WARNING
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|| | ||+---------------------------------> '1' : XDMGRPT
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|| | |+----------------------------------> '1' : DGRDRPT
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@@ -138,7 +138,7 @@
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/* External interrupt subclasses */
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/*
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/*
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* Adds ECPS:VM Vtimer which has no individual
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* subclass mask in CR0
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*/
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@@ -311,19 +311,27 @@
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#define ON_IC_IOPENDING \
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do { \
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int i; CPU_BITMAP mask; \
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if ( !(sysblk.ints_state & BIT(IC_IO)) ) { \
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REGS *regs; \
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CPU_BITMAP mask = sysblk.started_mask; \
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CPU_BITMAP wake; \
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int i; \
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if ( !(sysblk.ints_state & BIT(IC_IO)) ) \
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{ \
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sysblk.ints_state |= BIT(IC_IO); \
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mask = sysblk.started_mask; \
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for (i = 0; mask; i++) { \
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if (mask & 1) { \
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if ( sysblk.regs[i]->ints_mask & BIT(IC_IO) ) \
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sysblk.regs[i]->ints_state |= BIT(IC_INTERRUPT) | BIT(IC_IO); \
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wake = mask; \
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for (i = 0; mask; mask >>= 1, ++i) \
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{ \
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if (mask & 1) \
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{ \
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regs = sysblk.regs[i]; \
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if ( regs->ints_mask & BIT(IC_IO) ) \
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regs->ints_state |= BIT(IC_INTERRUPT) | BIT(IC_IO); \
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else \
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sysblk.regs[i]->ints_state |= BIT(IC_IO); \
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regs->ints_state |= BIT(IC_IO), \
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wake ^= regs->cpubit; \
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} \
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mask >>= 1; \
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} \
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WAKEUP_CPU_MASK(wake); \
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} \
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} while (0)
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