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https://github.com/SDL-Hercules-390/hyperion.git
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Cleanup "invalidate_pte" function:
All I did was replace some hard coded constants with #define constants instead and tweak some comments to try and make the function easier to follow/understand. There *should* be NO CHANGE in actual functionality. [skip travis] (more commits coming)
This commit is contained in:
Fish (David B. Trout)
@@ -1888,134 +1888,179 @@ void ARCH_DEP( invalidate_tlbe )( REGS* regs, BYTE* main )
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/*-------------------------------------------------------------------*/
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/* Invalidate page table entry */
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/* Invalidate Page Table Entry */
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/*-------------------------------------------------------------------*/
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/* */
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/* Input: */
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/* ibyte 0x21=IPTE instruction, 0x59=IESBE instruction */
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/* r1 First operand register number */
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/* r2 Second operand register number */
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/* This function is called by the IPTE and IESBE instructions. It */
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/* either sets the PAGETAB_INVALID bit (for IPTE instruction) or */
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/* resets the PAGETAB_ESVALID bit (for IESBE instruction) for the */
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/* Page Table Entry addressed by the passed Page Table Origin value */
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/* plus the Virtual Address's page index value, and clears the TLB */
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/* of all entries with a Page Frame Real Address matching the one */
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/* from the invalidated Page Table Entry. */
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/* */
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/* Input: */
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/* */
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/* ibyte 0x21 = IPTE instruction, 0x59 = IESBE instruction */
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/* pto Real address of Page Table Origin identifying the */
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/* Page Table containing the Entry to be invalidated */
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/* vaddr Virtual Address of page within specified Page Table */
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/* whose entry is to be invalidated */
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/* regs CPU register context */
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/* */
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/* This function is called by the IPTE and IESBE instructions. */
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/* It sets the PAGETAB_INVALID bit (for IPTE) or resets the */
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/* PAGETAB_ESVALID bit (for IESBE) in the page table entry */
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/* addressed by the page table origin in the R1 register and */
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/* the page index in the R2 register. It clears the TLB of */
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/* all entries whose PFRA matches the page table entry. */
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/* *** IMPORTANT! *** */
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/* */
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/* invalidate_pte should be called with the intlock held and */
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/* SYNCHRONIZE_CPUS issued while intlock is held. */
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/* This function expects INTLOCK to be held */
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/* and SYNCHRONIZE_CPUS to be called beforehand! */
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/* */
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/*-------------------------------------------------------------------*/
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void ARCH_DEP(invalidate_pte) (BYTE ibyte, RADR op1,
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U32 op2, REGS *regs)
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void ARCH_DEP( invalidate_pte )( BYTE ibyte, RADR pto, VADR vaddr, REGS* regs )
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{
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RADR raddr; /* Addr of page table entry */
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RADR pte;
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RADR pfra;
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RADR raddr; /* Addr of Page Table Entry */
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RADR pte; /* Page Table Entry itself */
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RADR pfra; /* Page Frame Real Address */
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UNREFERENCED_370( ibyte );
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#if !defined( FEATURE_S390_DAT ) && !defined( FEATURE_001_ZARCH_INSTALLED_FACILITY )
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{
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// SYSTEM/370...
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/* Program check if translation format is invalid */
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if ((((regs->CR(0) & CR0_PAGE_SIZE) != CR0_PAGE_SZ_2K) &&
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((regs->CR(0) & CR0_PAGE_SIZE) != CR0_PAGE_SZ_4K)) ||
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(((regs->CR(0) & CR0_SEG_SIZE) != CR0_SEG_SZ_64K) &&
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((regs->CR(0) & CR0_SEG_SIZE) != CR0_SEG_SZ_1M)))
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regs->program_interrupt (regs,
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PGM_TRANSLATION_SPECIFICATION_EXCEPTION);
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if (0
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|| (((regs->CR(0) & CR0_PAGE_SIZE) != CR0_PAGE_SZ_2K) && ((regs->CR(0) & CR0_PAGE_SIZE) != CR0_PAGE_SZ_4K))
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|| (((regs->CR(0) & CR0_SEG_SIZE) != CR0_SEG_SZ_64K) && ((regs->CR(0) & CR0_SEG_SIZE) != CR0_SEG_SZ_1M))
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)
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regs->program_interrupt( regs, PGM_TRANSLATION_SPECIFICATION_EXCEPTION );
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/* Combine the page table origin in the R1 register with
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the page index in the R2 register, ignoring carry, to
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form the 31-bit real address of the page table entry */
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raddr = (op1 & SEGTAB_370_PTO)
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+ (((regs->CR(0) & CR0_SEG_SIZE) == CR0_SEG_SZ_1M) ?
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(((regs->CR(0) & CR0_PAGE_SIZE) == CR0_PAGE_SZ_4K) ?
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((op2 & 0x000FF000) >> 11) :
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((op2 & 0x000FF800) >> 10)) :
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(((regs->CR(0) & CR0_PAGE_SIZE) == CR0_PAGE_SZ_4K) ?
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((op2 & 0x0000F000) >> 11) :
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((op2 & 0x0000F800) >> 10)));
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raddr &= 0x00FFFFFF;
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/* Add the vaddr's page table entry index to the Page Table
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Origin, ignoring any carry, to form the 24-bit real address
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of the Page Table Entry to be invalidated, taking into account
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that each Page Table Entry is 2 bytes wide (shift 1 less bit)
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*/
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raddr = (pto & SEGTAB_370_PTO) +
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(
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((regs->CR(0) & CR0_SEG_SIZE) == CR0_SEG_SZ_1M)
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?
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(((regs->CR(0) & CR0_PAGE_SIZE) == CR0_PAGE_SZ_4K) ?
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((vaddr & 0x000FF000) >> (SHIFT_4K-1)) : ((vaddr & 0x000FF800) >> (SHIFT_2K-1)))
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:
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(((regs->CR(0) & CR0_PAGE_SIZE) == CR0_PAGE_SZ_4K) ?
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((vaddr & 0x0000F000) >> (SHIFT_4K-1)) : ((vaddr & 0x0000F800) >> (SHIFT_2K-1)))
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);
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raddr &= MAXADDRESS;
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/* Fetch the page table entry from real storage, subject
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to normal storage protection mechanisms */
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pte = ARCH_DEP(vfetch2) ( raddr, USE_REAL_ADDR, regs );
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/* Fetch the Page Table Entry from real storage,
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subject to normal storage protection mechanisms
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*/
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pte = ARCH_DEP( vfetch2 )( raddr, USE_REAL_ADDR, regs );
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/* Set the page invalid bit in the page table entry,
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again subject to storage protection mechansims */
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// /*debug*/ LOGMSG("dat.c: IPTE issued for entry %4.4X at %8.8X...\n"
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// " page table %8.8X, page index %8.8X, cr0 %8.8X\n",
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// pte, raddr, regs->GR_L(r1), regs->GR_L(r2), regs->CR(0));
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if ((regs->CR(0) & CR0_PAGE_SIZE) == CR0_PAGE_SZ_2K)
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pte |= PAGETAB_INV_2K;
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else
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pte |= PAGETAB_INV_4K;
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ARCH_DEP(vstore2) ( pte, raddr, USE_REAL_ADDR, regs );
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pfra = ((regs->CR(0) & CR0_PAGE_SIZE) == CR0_PAGE_SZ_4K) ?
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#if 0 // debug 370 IPTE
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LOGMSG
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(
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"dat.c: IPTE issued for entry %4.4X at %8.8X...\n"
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" pto %8.8X, vaddr %8.8X, cr0 %8.8X\n"
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, pte, raddr
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, pto, vaddr, regs->CR(0)
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);
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#endif
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/* Set the invalid bit in the Page Table Entry just fetched */
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pte |= ((regs->CR(0) & CR0_PAGE_SIZE) == CR0_PAGE_SZ_2K)
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? PAGETAB_INV_2K : PAGETAB_INV_4K;
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/* Store the now invalidated Page Table Entry back into
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real storage where we originally got it from, subject
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to the same storage protection mechanisms
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*/
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ARCH_DEP( vstore2 )( pte, raddr, USE_REAL_ADDR, regs );
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/* Extract the Page Frame Address from the Page Table Entry */
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pfra = ((regs->CR(0) & CR0_PAGE_SIZE) == CR0_PAGE_SZ_4K)
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?
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#if defined( FEATURE_S370E_EXTENDED_ADDRESSING )
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(((U32)pte & PAGETAB_EA_4K) << 23) |
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#endif
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(((U32)pte & PAGETAB_PFRA_4K) << 8) :
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(((U32)pte & PAGETAB_PFRA_4K) << 8)
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:
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(((U32)pte & PAGETAB_PFRA_2K) << 8);
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}
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#elif defined( FEATURE_S390_DAT )
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{
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// SYSTEM/390...
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/* Program check if translation format is invalid */
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if ((regs->CR(0) & CR0_TRAN_FMT) != CR0_TRAN_ESA390)
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regs->program_interrupt (regs,
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PGM_TRANSLATION_SPECIFICATION_EXCEPTION);
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regs->program_interrupt( regs, PGM_TRANSLATION_SPECIFICATION_EXCEPTION );
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/* Combine the page table origin in the R1 register with
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the page index in the R2 register, ignoring carry, to
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form the 31-bit real address of the page table entry */
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raddr = (op1 & SEGTAB_PTO)
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+ ((op2 & 0x000FF000) >> 10);
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raddr &= 0x7FFFFFFF;
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/* Add the vaddr's page table entry index to the Page Table
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Origin, ignoring any carry, to form the 31-bit real address
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of the Page Table Entry to be invalidated, taking into account
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that each Page Table Entry is 4 bytes wide (shift 2 fewer bits)
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*/
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raddr = (pto & SEGTAB_PTO) + ((vaddr & 0x000FF000) >> (PAGEFRAME_PAGESHIFT-2));
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raddr &= MAXADDRESS;
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/* Fetch the page table entry from real storage, subject
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to normal storage protection mechanisms */
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pte = ARCH_DEP(vfetch4) ( raddr, USE_REAL_ADDR, regs );
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/* Fetch the Page Table Entry from real storage,
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subject to normal storage protection mechanisms */
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pte = ARCH_DEP( vfetch4 )( raddr, USE_REAL_ADDR, regs );
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/* Set the page invalid bit in the page table entry,
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again subject to storage protection mechansims */
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/* Set the invalid bit in the Page Table Entry just fetched */
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#if defined( FEATURE_MOVE_PAGE_FACILITY_2 ) && defined( FEATURE_EXPANDED_STORAGE )
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if(ibyte == 0x59)
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if (ibyte == 0x59) // (IESBE instruction?)
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pte &= ~PAGETAB_ESVALID;
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else
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#endif
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pte |= PAGETAB_INVALID;
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ARCH_DEP(vstore4) ( pte, raddr, USE_REAL_ADDR, regs );
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pte |= PAGETAB_INVALID; // (no, IPTE instruction)
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/* Store the now invalidated Page Table Entry back into
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real storage where we originally got it from, subject
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to the same storage protection mechanisms
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*/
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ARCH_DEP( vstore4 )( pte, raddr, USE_REAL_ADDR, regs );
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/* Extract the Page Frame Address from the Page Table Entry */
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pfra = pte & PAGETAB_PFRA;
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}
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#else /* defined( FEATURE_001_ZARCH_INSTALLED_FACILITY ) */
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{
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/* Combine the page table origin in the R1 register with
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the page index in the R2 register, ignoring carry, to
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form the 64-bit real address of the page table entry */
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raddr = (op1 & ZSEGTAB_PTO)
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+ ((op2 & 0x000FF000) >> 9);
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// ESAME = z/Architecture...
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/* Fetch the page table entry from real storage, subject
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to normal storage protection mechanisms */
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pte = ARCH_DEP(vfetch8) ( raddr, USE_REAL_ADDR, regs );
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/* Add the vaddr's page table entry index to the Page Table
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Origin, ignoring any carry, to form the 64-bit real address
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of the Page Table Entry to be invalidated, taking into account
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that each Page Table Entry is 8 bytes wide (shift 3 fewer bits)
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*/
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raddr = (pto & ZSEGTAB_PTO) + ((vaddr & 0x000FF000) >> (PAGEFRAME_PAGESHIFT-3));
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raddr &= MAXADDRESS;
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/* Set the page invalid bit in the page table entry,
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again subject to storage protection mechansims */
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/* Fetch the Page Table Entry from real storage,
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subject to normal storage protection mechanisms
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*/
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pte = ARCH_DEP( vfetch8 )( raddr, USE_REAL_ADDR, regs );
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/* Set the invalid bit in the Page Table Entry just fetched */
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#if defined( FEATURE_MOVE_PAGE_FACILITY_2 ) && defined( FEATURE_EXPANDED_STORAGE )
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if(ibyte == 0x59)
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if (ibyte == 0x59) // (IESBE instruction?)
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pte &= ~ZPGETAB_ESVALID;
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else
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#endif
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pte |= ZPGETAB_I;
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ARCH_DEP(vstore8) ( pte, raddr, USE_REAL_ADDR, regs );
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pte |= ZPGETAB_I; // (no, IPTE instruction)
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/* Store the now invalidated Page Table Entry back into
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real storage where we originally got it from, subject
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to the same storage protection mechanisms
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*/
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ARCH_DEP( vstore8 )( pte, raddr, USE_REAL_ADDR, regs );
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/* Extract the Page Frame Address from the Page Table Entry */
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pfra = pte & ZPGETAB_PFRA;
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}
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#endif /* defined( FEATURE_001_ZARCH_INSTALLED_FACILITY ) */
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/* Invalidate TLB entries */
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ARCH_DEP(purge_tlbe_all) (pfra);
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/* Invalidate all TLB entries for this Page Frame Real Address */
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ARCH_DEP( purge_tlbe_all )( pfra );
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} /* end function invalidate_pte */
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