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Move structures - no functional change

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This commit is contained in:
Jan Jaeger
2012-04-13 14:29:12 +10:00
parent 61dee07eef
commit e308ca6fb4
9 changed files with 699 additions and 713 deletions
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Makefile.am
+4 -1
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@@ -93,6 +93,7 @@ dyndev_SRC = commadpt.c \
tuntap.c \
resolve.c \
qeth.c \
mpc.c \
con1052c.c
@@ -254,7 +255,7 @@ if OPTION_DYNAMIC_LOAD
hdt3525_la_LDFLAGS = $(DYNMOD_LD_FLAGS)
hdt3525_la_LIBADD = $(DYNMOD_LD_ADD)
hdtqeth_la_SOURCES = qeth.c tuntap.c
hdtqeth_la_SOURCES = qeth.c mpc.c tuntap.c
hdtqeth_la_LDFLAGS = $(DYNMOD_LD_FLAGS)
hdtqeth_la_LIBADD = $(DYNMOD_LD_ADD)
@@ -735,6 +736,8 @@ noinst_HEADERS = fishhang.h \
service.h \
chsc.h \
qeth.h \
qdio.h \
mpc.h \
pttrace.h \
history.h \
sr.h \
esa390.h
+16 -16
View File
@@ -1014,22 +1014,22 @@ typedef struct _ORB {
/* Path management control word structure definition */
typedef struct _PMCW {
FWORD intparm; /* Interruption parameter */
BYTE flag4; /* Flag byte 4 */
BYTE flag5; /* Flag byte 5 */
HWORD devnum; /* Device number */
BYTE lpm; /* Logical path mask */
BYTE pnom; /* Path not operational mask */
BYTE lpum; /* Last path used mask */
BYTE pim; /* Path installed mask */
HWORD mbi; /* Measurement block index */
BYTE pom; /* Path operational mask */
BYTE pam; /* Path available mask */
BYTE chpid[8]; /* Channel path identifiers */
BYTE zone; /* SIE zone */
BYTE flag25; /* Flag byte 25 */
BYTE flag26; /* Reserved byte - must be 0 */
BYTE flag27; /* Flag byte 27 */
/*000*/ FWORD intparm; /* Interruption parameter */
/*004*/ BYTE flag4; /* Flag byte 4 */
/*005*/ BYTE flag5; /* Flag byte 5 */
/*006*/ HWORD devnum; /* Device number */
/*008*/ BYTE lpm; /* Logical path mask */
/*009*/ BYTE pnom; /* Path not operational mask */
/*00A*/ BYTE lpum; /* Last path used mask */
/*00B*/ BYTE pim; /* Path installed mask */
/*00C*/ HWORD mbi; /* Measurement block index */
/*00E*/ BYTE pom; /* Path operational mask */
/*00F*/ BYTE pam; /* Path available mask */
/*010*/ BYTE chpid[8]; /* Channel path identifiers */
/*018*/ BYTE zone; /* SIE zone */
/*019*/ BYTE flag25; /* Flag byte 25 */
/*01A*/ BYTE flag26; /* Reserved byte - must be 0 */
/*01B*/ BYTE flag27; /* Flag byte 27 */
} PMCW;
/* Bit definitions for PMCW flag byte 4 */
hercules.h
+1
View File
@@ -115,6 +115,7 @@
#include "clock.h" // (TOD definitions)
#include "qeth.h" // (QETH device definitions)
#include "qdio.h" // (QDIO device definitions)
#include "codepage.h"
#include "logger.h" // (logmsg, etc)
mpc.c
+22
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@@ -0,0 +1,22 @@
/* MPC.C (c) Copyright Jan Jaeger, 2010-2012 */
/* (c) Copyright Ian Shorter, 2011-2012 */
/* (c) Copyright Harold Grovesteen, 2011-2012 */
/* MPC */
/* This implementation is based on the S/390 Linux implementation */
#include "hstdinc.h"
#if !defined(_HENGINE_DLL_)
#define _HENGINE_DLL_
#endif
#if !defined(_MPC_C_)
#define _MPC_C_
#endif
#include "hercules.h"
#include "mpc.h"
mpc.h
+354
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@@ -0,0 +1,354 @@
/* MPC.H (c) Copyright Jan Jaeger, 2010-2012 */
/* (c) Copyright Ian Shorter, 2011-2012 */
/* (c) Copyright Harold Grovesteen, 2011-2012 */
/* MPC */
/* This implementation is based on the S/390 Linux implementation */
#if !defined(_MPC_H)
#define _MPC_H
/*-------------------------------------------------------------------*/
/* Header for MPC command frames */
/*-------------------------------------------------------------------*/
typedef struct _MPC_HDR {
/*000*/ HWORD resv000; /* */
/*002*/ HWORD ddc; /* Device Directed Command */
#define IDX_ACT_DDC 0x8000
/*004*/ FWORD thsn; /* Transport Header Sequence Number */
} MPC_HDR;
/*-------------------------------------------------------------------*/
/* Identification Exchange Activate */
/*-------------------------------------------------------------------*/
typedef struct _MPC_IEA {
/*000*/ MPC_HDR hdr;
/*008*/ HWORD type; /* IDX_ACT type (read or write) */
#define IDX_ACT_TYPE_READ 0x1901
#define IDX_ACT_TYPE_WRITE 0x1501
/*00A*/ BYTE resv00a; /* */
#define IDX_ACT_RESV00A 0x01
/*00B*/ BYTE port; /* Port number (bit 0 set) */
#define IDX_ACT_PORT_MASK 0x3F
#define IDX_ACT_PORT_ACTIVATE 0x80
#define IDX_ACT_PORT_STANDBY 0x40
/*00C*/ FWORD token; /* Issuer token */
/*010*/ HWORD flevel; /* Function level */
#define IDX_ACT_FLEVEL_READ 0x0000
#define IDX_ACT_FLEVEL_WRITE 0xFFFF
/*012*/ FWORD uclevel; /* Microcode level */
/*016*/ BYTE dataset[8]; /* Portname */
/*01E*/ HWORD datadev; /* Data Device Number */
/*020*/ BYTE ddcua; /* Data Device Control Unit Address */
/*021*/ BYTE ddua; /* Data Device Unit Address */
} MPC_IEA;
/*-------------------------------------------------------------------*/
/* Identification Exchange Activate Response */
/*-------------------------------------------------------------------*/
typedef struct _MPC_IEAR {
/*000*/ HWORD resv000; /* */
/*002*/ BYTE cmd; /* Response code */
#define IDX_RSP_CMD_MASK 0xC0
#define IDX_RSP_CMD_TERM 0xC0 /* IDX_TERMINATE received */
/*003*/ BYTE resv003; /* */
/*004*/ BYTE reason; /* Reason code */
#define IDX_RSP_REASON_INVPORT 0x22
/*005*/ BYTE resv005[3]; /* */
/*008*/ BYTE resp; /* Response code */
#define IDX_RSP_RESP_MASK 0x03
#define IDX_RSP_RESP_OK 0x02
/*009*/ BYTE cause; /* Negative response cause code */
#define IDX_RSP_CAUSE_INUSE 0x19
/*00A*/ BYTE resv010; /* */
/*00B*/ BYTE flags; /* Flags */
#define IDX_RSP_FLAGS_NOPORTREQ 0x80
/*00C*/ FWORD token; /* Issues rm_r token */
/*010*/ HWORD flevel; /* Funtion level */
/*012*/ FWORD uclevel; /* Microcode level */
} MPC_IEAR;
/*-------------------------------------------------------------------*/
/* Transport Header */
/*-------------------------------------------------------------------*/
typedef struct _MPC_TH {
/*000*/ MPC_HDR hdr;
/*008*/ HWORD resv008; /* */
/*00A*/ HWORD rroff; /* Offset to request/response struct */
/*00C*/ HWORD resv00c; /* */
/*00E*/ HWORD rrlen; /* Length of request/response struct */
/*010*/ FWORD end; /* X'10000001' */
} MPC_TH;
/*-------------------------------------------------------------------*/
/* Request/Response Header */
/*-------------------------------------------------------------------*/
typedef struct _MPC_RRH {
/*000*/ FWORD resv000; /* */
/*004*/ BYTE type; /* Request type */
#define RRH_TYPE_CM 0x81
#define RRH_TYPE_ULP 0x41
#define RRH_TYPE_IPA 0xC1
/*005*/ BYTE proto; /* Protocol type */
#define RRH_PROTO_L2 0x08
#define RRH_PROTO_L3 0x03
#define RRH_PROTO_NCP 0x0A
#define RRH_PROTO_UNK 0x7E
/*006*/ HWORD unkn006; /* X'0001' */
/*008*/ FWORD pduseq; /* PDU Sequence Number */
/*00C*/ FWORD ackseq; /* ACK Sequence Number */
/*010*/ HWORD pduhoff; /* Offset to PDU Header */
/*012*/ HWORD pduhlen; /* Length of PDU Header */
/*014*/ BYTE resv014; /* */
/*015*/ HWORD reqlen; /* Request length */
/*017*/ BYTE unkn016; /* X'05' */
/*018*/ FWORD token; /* */
/*01C*/ FWORD resv020; /* */
/*020*/ FWORD resv024; /* */
} MPC_RRH;
/*-------------------------------------------------------------------*/
/* Protocol Data Unit Header */
/*-------------------------------------------------------------------*/
typedef struct _MPC_PH {
/*000*/ HWORD type; /* */
/*002*/ HWORD pdulen; /* Length of request */
/*004*/ HWORD resv004; /* */
/*006*/ HWORD hdrlen; /* Total Header lenght */
} MPC_PH;
/*-------------------------------------------------------------------*/
/* Protocol Data Unit */
/*-------------------------------------------------------------------*/
typedef struct _MPC_PDU {
/*000*/ HWORD len; /* */
/*002*/ BYTE tgt; /* Command target */
#define PDU_TGT_OSA 0x41
#define PDU_TGT_QDIO 0x43
/*003*/ BYTE cmd; /* Command */
#define PDU_CMD_ENABLE 0x02
#define PDU_CMD_SETUP 0x04
#define PDU_CMD_ACTIVATE 0x60
/*004*/ HWORD rlen; /* Request length */
/*006*/ HWORD resv006; /* */
/*008*/ FWORD resv008; /* */
/*00C*/ HWORD ilen; /* */
/*00E*/ BYTE unkn00e; /* */
/*00F*/ BYTE unkn00f; /* */
/*010*/ BYTE proto; /* */
#define PDU_PROTO_L2 0x08
#define PDU_PROTO_L3 0x03
#define PDU_PROTO_NCP 0x0A
#define PDU_PROTO_UNK 0x7E
// ZZ INCOMPLETE
} MPC_PDU;
/*-------------------------------------------------------------------*/
/* IP Assist Header */
/*-------------------------------------------------------------------*/
typedef struct _MPC_IPA {
/*000*/ BYTE cmd; /* Command */
/*001*/ BYTE iid; /* Initator Identifier */
#define IPA_IID_HOST 0x00
#define IPA_IID_ADAPTER 0x01
#define IPA_IID_REPLY 0x80
/*002*/ HWORD seq; /* Sequence number */
/*004*/ HWORD rc; /* Return Code */
#define IPA_RC_OK IPA_RC_SUCCESS
/*006*/ BYTE at; /* Adapter Type */
#define IPA_AT_ANY 0x01
/*007*/ BYTE port; /* OSA Port Number */
/*008*/ BYTE lvl; /* OSA Level */
#define IPA_LVL_ANY 0x01
#define IPA_LVL_L2 0x02
/*009*/ BYTE cnt; /* Parameter Count */
/*00A*/ HWORD proto; /* Protocol */
#define IPA_PROTO_ANY 0x0000
#define IPA_PROTO_IPV4 0x0004
#define IPA_PROTO_IPV6 0x0006
/*00C*/ FWORD ipas; /* Supported IP Assist mask */
/*010*/ FWORD ipae; /* Enabled IP Assist mask */
} MPC_IPA;
#define IPA_ARP_PROCESSING 0x00000001L
#define IPA_INBOUND_CHECKSUM 0x00000002L
#define IPA_OUTBOUND_CHECKSUM 0x00000004L
#define IPA_IP_FRAGMENTATION 0x00000008L
#define IPA_FILTERING 0x00000010L
#define IPA_IPV6 0x00000020L
#define IPA_MULTICASTING 0x00000040L
#define IPA_IP_REASSEMBLY 0x00000080L
#define IPA_QUERY_ARP_COUNTERS 0x00000100L
#define IPA_QUERY_ARP_ADDR_INFO 0x00000200L
#define IPA_SETADAPTERPARMS 0x00000400L
#define IPA_VLAN_PRIO 0x00000800L
#define IPA_PASSTHRU 0x00001000L
#define IPA_FLUSH_ARP_SUPPORT 0x00002000L
#define IPA_FULL_VLAN 0x00004000L
#define IPA_INBOUND_PASSTHRU 0x00008000L
#define IPA_SOURCE_MAC 0x00010000L
#define IPA_OSA_MC_ROUTER 0x00020000L
#define IPA_QUERY_ARP_ASSIST 0x00040000L
#define IPA_INBOUND_TSO 0x00080000L
#define IPA_OUTBOUND_TSO 0x00100000L
#define IPA_SUPP ( 0 \
| IPA_PASSTHRU \
| IPA_INBOUND_PASSTHRU \
)
#define IPA_CMD_STARTLAN 0x01 /* Start LAN operations */
#define IPA_CMD_STOPLAN 0x02 /* Stop LAN operations */
#define IPA_CMD_SETVMAC 0x21 /* Set Layer-2 MAC address */
#define IPA_CMD_DELVMAC 0x22 /* Delete Layer-2 MAC address */
#define IPA_CMD_SETGMAC 0x23 /* Set Layer-2 Group Multicast addr */
#define IPA_CMD_DELGMAC 0x24 /* Del Layer-2 Group Multicast addr */
#define IPA_CMD_SETVLAN 0x25 /* Set Layer-2 VLAN */
#define IPA_CMD_DELVLAN 0x26 /* Delete Layer-2 VLAN */
#define IPA_CMD_SETCCID 0x41 /* */
#define IPA_CMD_DELCCID 0x42 /* */
#define IPA_CMD_MODCCID 0x43 /* */
#define IPA_CMD_SETIP 0xB1 /* Set Layer-3 IP unicast address */
#define IPA_CMD_QIPASSIST 0xB2 /* Query Layer-3 IP assist capability*/
#define IPA_CMD_SETASSPARMS 0xB3 /* Set Layer-3 IP assist parameters */
#define IPA_CMD_SETIPM 0xB4 /* Set Layer-3 IP multicast address */
#define IPA_CMD_DELIPM 0xB5 /* Delete Layer-3 IP multicast addr */
#define IPA_CMD_SETRTG 0xB6 /* Set Layer-3 routing information */
#define IPA_CMD_DELIP 0xB7 /* Delete Layer-3 IP unicast addr */
#define IPA_CMD_SETADPPARMS 0xB8 /* Various adapter directed sub-cmds*/
#define IPA_CMD_SETDIAGASS 0xB9 /* Set Layer-3 diagnostic assists */
#define IPA_CMD_CREATEADDR 0xC3 /* Create L3 IPv6 addr from L2 MAC */
#define IPA_CMD_DESTROYADDR 0xC4 /* Destroy L3 IPv6 addr from L2 MAC */
#define IPA_CMD_REGLCLADDR 0xD1 /* */
#define IPA_CMD_UNREGLCLADDR 0xD2 /* */
#define IPA_RC_SUCCESS 0x0000
#define IPA_RC_NOTSUPP 0x0001
#define IPA_RC_IP_TABLE_FULL 0x0002
#define IPA_RC_UNKNOWN_ERROR 0x0003
#define IPA_RC_UNSUPPORTED_COMMAND 0x0004
#define IPA_RC_TRACE_ALREADY_ACTIVE 0x0005
#define IPA_RC_INVALID_FORMAT 0x0006
#define IPA_RC_DUP_IPV6_REMOTE 0x0008
#define IPA_RC_DUP_IPV6_HOME 0x0010
#define IPA_RC_UNREGISTERED_ADDR 0x0011
#define IPA_RC_NO_ID_AVAILABLE 0x0012
#define IPA_RC_ID_NOT_FOUND 0x0013
#define IPA_RC_INVALID_IP_VERSION 0x0020
#define IPA_RC_LAN_FRAME_MISMATCH 0x0040
#define IPA_RC_L2_UNSUPPORTED_CMD 0x2003
#define IPA_RC_L2_DUP_MAC 0x2005
#define IPA_RC_L2_ADDR_TABLE_FULL 0x2006
#define IPA_RC_L2_DUP_LAYER3_MAC 0x200a
#define IPA_RC_L2_GMAC_NOT_FOUND 0x200b
#define IPA_RC_L2_MAC_NOT_AUTH_BY_HYP 0x200c
#define IPA_RC_L2_MAC_NOT_AUTH_BY_ADP 0x200d
#define IPA_RC_L2_MAC_NOT_FOUND 0x2010
#define IPA_RC_L2_INVALID_VLAN_ID 0x2015
#define IPA_RC_L2_DUP_VLAN_ID 0x2016
#define IPA_RC_L2_VLAN_ID_NOT_FOUND 0x2017
#define IPA_RC_DATA_MISMATCH 0xe001
#define IPA_RC_INVALID_MTU_SIZE 0xe002
#define IPA_RC_INVALID_LANTYPE 0xe003
#define IPA_RC_INVALID_LANNUM 0xe004
#define IPA_RC_DUPLICATE_IP_ADDRESS 0xe005
#define IPA_RC_IP_ADDR_TABLE_FULL 0xe006
#define IPA_RC_LAN_PORT_STATE_ERROR 0xe007
#define IPA_RC_SETIP_NO_STARTLAN 0xe008
#define IPA_RC_SETIP_ALREADY_RECEIVED 0xe009
#define IPA_RC_IP_ADDR_ALREADY_USED 0xe00a
#define IPA_RC_MC_ADDR_NOT_FOUND 0xe00b
#define IPA_RC_SETIP_INVALID_VERSION 0xe00d
#define IPA_RC_UNSUPPORTED_SUBCMD 0xe00e
#define IPA_RC_ARP_ASSIST_NO_ENABLE 0xe00f
#define IPA_RC_PRIMARY_ALREADY_DEFINED 0xe010
#define IPA_RC_SECOND_ALREADY_DEFINED 0xe011
#define IPA_RC_INVALID_SETRTG_INDICATOR 0xe012
#define IPA_RC_MC_ADDR_ALREADY_DEFINED 0xe013
#define IPA_RC_LAN_OFFLINE 0xe080
#define IPA_RC_INVALID_IP_VERSION2 0xf001
#define IPA_RC_FFFF 0xffff
/*-------------------------------------------------------------------*/
/* MAC request */
/*-------------------------------------------------------------------*/
typedef struct _MPC_IPA_MAC {
/*000*/ FWORD maclen; /* Length of MAC Address */
/*004*/ BYTE macaddr[FLEXIBLE_ARRAY]; /* MAC Address */
} MPC_IPA_MAC;
/*-------------------------------------------------------------------*/
/* Set Adapter Parameters */
/*-------------------------------------------------------------------*/
typedef struct _MPC_IPA_SAP {
/*000*/ FWORD suppcm; /* Supported subcommand mask */
#define IPA_SAP_QUERY 0x00000001L
#define IPA_SAP_SETMAC 0x00000002L
#define IPA_SAP_SETGADR 0x00000004L
#define IPA_SAP_SETFADR 0x00000008L
#define IPA_SAP_SETAMODE 0x00000010L
#define IPA_SAP_SETCFG 0x00000020L
#define IPA_SAP_SETCFGE 0x00000040L
#define IPA_SAP_BRDCST 0x00000080L
#define IPA_SAP_OSAMSG 0x00000100L
#define IPA_SAP_SETSNMP 0x00000200L
#define IPA_SAP_CARDINFO 0x00000400L
#define IPA_SAP_PROMISC 0x00000800L
#define IPA_SAP_SETDIAG 0x00002000L
#define IPA_SAP_SETACCESS 0x00010000L
#define IPA_SAP_SUPP ( 0 \
| IPA_SAP_QUERY \
| IPA_SAP_PROMISC \
)
/*004*/ FWORD resv004; /* */
/*008*/ HWORD cmdlen; /* Subcommand length */
/*00A*/ HWORD resv00a; /* */
/*00C*/ FWORD cmd; /* Subcommand */
/*010*/ HWORD rc; /* Return Code */
/*012*/ BYTE used; /* */
/*013*/ BYTE seqno; /* */
/*014*/ FWORD resv014; /* */
} MPC_IPA_SAP;
/*-------------------------------------------------------------------*/
/* SAP ADP Qeury */
/*-------------------------------------------------------------------*/
typedef struct _SAP_QRY {
/*000*/ FWORD nlan; /* Number of Lan types supported */
/*004*/ BYTE rsp; /* LAN type response */
/*005*/ BYTE resv005[3];
/*008*/ FWORD suppcm; /* Supported commands bit map */
/*00A*/ DBLWRD resv00a;
} SAP_QRY;
/*-------------------------------------------------------------------*/
/* Set Promiscuous Mode on/off */
/*-------------------------------------------------------------------*/
typedef struct _SAP_SPM {
/*000*/ FWORD promisc; /* Promiscuous mode */
#define SAP_PROMISC_ON 0x00000001
#define SAP_PROMISC_OFF 0x00000000
} SAP_SPM;
#endif /*!defined(_MPC_H)*/
qdio.c
+1 -9
View File
@@ -20,7 +20,7 @@
#include "opcode.h"
#include "qeth.h"
#include "qdio.h"
#include "inline.h"
@@ -176,7 +176,6 @@ int b2; /* effective address base */
VADR effective_addr2; /* effective address */
DEVBLK *dev; /* Data device DEVBLK */
OSA_GRP *grp; /* OSA Group device structure */
BYTE state; /* Target buffer state */
BYTE oldstate; /* Current buffer state */
@@ -229,9 +228,6 @@ U64 slsba; /* Storage list state block address */
}
#endif
/* Locate the group device block */
grp = (OSA_GRP*)dev->group->grp_data;
qidx = regs->GR_H(r1); /* Queue index */
bidx = regs->GR_L(r1); /* Buffer index */
count = regs->GR_L(r3) < 128 ? regs->GR_L(r3) : 128; /* Number of buffers */
@@ -278,7 +274,6 @@ int r1, r2, r3, m4; /* Register numbers */
VADR effective_addr2 = 0; /* effective address */
DEVBLK *dev; /* Data device DEVBLK */
OSA_GRP *grp; /* OSA Group device structure */
int autoack; /* Flag for auto-acknowkledgement */
BYTE state; /* State extracted from first buffer */
@@ -331,9 +326,6 @@ U64 slsba; /* Storage list state block address */
}
#endif
/* Locate the group device block */
grp = (OSA_GRP*)dev->group->grp_data;
qidx = regs->GR_H(r1); /* Queue index */
bidx = regs->GR_L(r1); /* Buffer index */
autoack = (regs->GR_H(r2) & 0x80000000);
qdio.h
+224
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@@ -0,0 +1,224 @@
/* QDIO.H (c) Copyright Jan Jaeger, 2010-2012 */
/* Queued Direct I/O */
/* This implementation is based on the S/390 Linux implementation */
#if !defined(_QDIO_H)
#define _QDIO_H
/*-------------------------------------------------------------------*/
/* OSA Device Structure */
/*-------------------------------------------------------------------*/
typedef struct _QDIO_DEV {
unsigned rxcnt; /* Receive count */
unsigned txcnt; /* Transmit count */
int idxstate; /* IDX state */
#define MPC_IDX_STATE_INACTIVE 0x00 // ZZ THIS FIELD NEEDS TO MOVE
#define MPC_IDX_STATE_ACTIVE 0x01
int thinint; /* Thin Interrupts on PCI */
int i_qcnt; /* Input Queue Count */
int i_qpos; /* Current Queue Position */
int i_bpos[QDIO_MAXQ]; /* Current Buffer Position */
int o_qcnt; /* Output Queue Count */
int o_qpos; /* Current Queue Position */
int o_bpos[QDIO_MAXQ]; /* Current Buffer Position */
U32 i_qmask; /* Input Queue Mask */
U32 o_qmask; /* Output Queue Mask */
BYTE i_slibk[QDIO_MAXQ]; /* Input SLIB Key */
BYTE i_slk[QDIO_MAXQ]; /* Input Storage List Key */
BYTE i_sbalk[QDIO_MAXQ]; /* Input SBAL Key */
BYTE i_slsblk[QDIO_MAXQ]; /* Input SLSB Key */
U64 i_sliba[QDIO_MAXQ]; /* Input SLIB Address */
U64 i_sla[QDIO_MAXQ]; /* Input Storage List Address */
U64 i_slsbla[QDIO_MAXQ]; /* Input SLSB Address */
BYTE o_slibk[QDIO_MAXQ]; /* Output SLIB Key */
BYTE o_slk[QDIO_MAXQ]; /* Output Storage List Key */
BYTE o_sbalk[QDIO_MAXQ]; /* Output SBAL Key */
BYTE o_slsblk[QDIO_MAXQ]; /* Output SLSB Key */
U64 o_sliba[QDIO_MAXQ]; /* Output SLIB Address */
U64 o_sla[QDIO_MAXQ]; /* Output Storage List Address */
U64 o_slsbla[QDIO_MAXQ]; /* Output SLSB Address */
BYTE qibk; /* Queue Information Block Key */
U64 qiba; /* Queue Information Block Address */
U64 alsi; /* Adapter Local Summ Indicator */
#define ALSI_ERROR 0x80 /* ZZ TO BE CONFIRMED */
U64 dsci; /* Device status change Indicator */
#define DSCI_IOCOMP 0x01 /* ZZ TO BE CONFIRMED */
BYTE ks; /* alsi storage key */
BYTE kc; /* dsci storage key */
} QDIO_DEV;
/*-------------------------------------------------------------------*/
/* Queue Descriptor Entry (Format 0) */
/*-------------------------------------------------------------------*/
typedef struct _QDIO_QDES0 {
/*000*/ DBLWRD sliba; /* Storage List Info Block Address */
/*008*/ DBLWRD sla; /* Storage List Address */
/*010*/ DBLWRD slsba; /* Storage List State Block Address */
/*018*/ FWORD resv018;
/*01C*/ BYTE keyp1; /* Access keys for SLIB and SL */
#define QDES_KEYP1_A_SLIB 0xF0
#define QDES_KEYP1_A_SL 0x0F
/*01D*/ BYTE keyp2; /* Access keys for SBALs ad SLSB */
#define QDES_KEYP2_A_SBAL 0xF0
#define QDES_KEYP2_A_SLSB 0x0F
/*01E*/ HWORD resv01e;
} QDIO_QDES0;
/*-------------------------------------------------------------------*/
/* Queue Descriptor Record (QDR) */
/*-------------------------------------------------------------------*/
typedef struct _QDIO_QDR {
/*000*/ BYTE qfmt; /* Queue Format */
/*001*/ BYTE pfmt; /* Model Dependent Parameter Format */
/*002*/ BYTE resv002;
/*003*/ BYTE ac; /* Adapter Characteristics */
/*004*/ BYTE resv004;
/*005*/ BYTE iqdcnt; /* Input Queue Descriptor Count */
/*006*/ BYTE resv006;
/*007*/ BYTE oqdcnt; /* Output Queue Descriptor Count */
/*008*/ BYTE resv008;
/*009*/ BYTE iqdsz; /* Input Queue Descriptor Size */
/*00A*/ BYTE resv00a;
/*00B*/ BYTE oqdsz; /* Output Queue Descriptor Size */
/*00C*/ FWORD resv00c[9];
/*030*/ DBLWRD qiba; /* Queue Information Block Address */
/*038*/ FWORD resv038;
/*03C*/ BYTE qkey; /* Queue Information Block Key */
/*03D*/ BYTE resv03d[3];
/*040*/ QDIO_QDES0 qdf0[126]; /* Format 0 Queue Descriptors */
} QDIO_QDR;
/*-------------------------------------------------------------------*/
/* Queue Information Block (QIB) */
/*-------------------------------------------------------------------*/
typedef struct _QDIO_QIB {
/*000*/ BYTE qfmt; /* Queue Format */
/*001*/ BYTE pfmt; /* Parameter Format */
#define QID_PFMT_QETH 0x00
/*002*/ BYTE rflags; /* Flags */
#define QIB_RFLAGS_QEBSM 0x80
/*003*/ BYTE ac; /* Adapter Characteristics */
#define QIB_AC_PCI 0x40
/*004*/ FWORD resv004;
/*008*/ DBLWRD isliba; /* Input SLIB queue address */
/*010*/ DBLWRD osliba; /* Output SLIB queue address */
/*018*/ FWORD resv018;
/*01C*/ FWORD resv01c;
/*020*/ BYTE ebcnam[8]; /* Adapter ID in EBCDIC */
/*028*/ BYTE resv028[88];
/*080*/ BYTE parm[128]; /* Model Dependent Parameters */
} QDIO_QIB;
/*-------------------------------------------------------------------*/
/* Storage List Information Block (SLIB) */
/*-------------------------------------------------------------------*/
typedef struct _QDIO_SLIB {
/*000*/ DBLWRD nsliba; /* Next SLIB in queue */
/*008*/ DBLWRD sla; /* Storage List Address */
/*010*/ DBLWRD slsba; /* Storage List State Block Address */
/*018*/ BYTE resv018[1000];
/*400*/ DBLWRD slibe[128]; /* Storage List Info Block Entry */
} QDIO_SLIB;
/*-------------------------------------------------------------------*/
/* Storage List (SL) */
/*-------------------------------------------------------------------*/
typedef struct _QDIO_SL {
/*000*/ DBLWRD sbala[128]; /* Storage Block Address List address*/
} QDIO_SL;
/*-------------------------------------------------------------------*/
/* Storage Block Address List Entry (SBALE) */
/*-------------------------------------------------------------------*/
typedef struct _QDIO_SBALE {
/*000*/ BYTE flags[4]; /* Flags */
#define SBAL_FLAGS0_LAST_ENTRY 0x40
#define SBAL_FLAGS0_CONTIGUOUS 0x20
#define SBAL_FLAGS0_FRAG_MASK 0x0C
#define SBAL_FLAGS0_FRAG_FIRST 0x04
#define SBAL_FLAGS0_FRAG_MIDDLE 0x08
#define SBAL_FLAGS0_FRAG_LAST 0x0C
#define SBAL_FLAGS1_PCI_REQ 0x40
/*004*/ FWORD length; /* Storage length */
/*008*/ DBLWRD addr; /* Storage Address */
} QDIO_SBALE;
/*-------------------------------------------------------------------*/
/* Storage Block Address List (SBAL) */
/*-------------------------------------------------------------------*/
typedef struct _QDIO_SBAL {
/*000*/ QDIO_SBALE sbale[16]; /* Storage Block Address List entry */
} QDIO_SBAL;
/*-------------------------------------------------------------------*/
/* Storage List State Block (SLSB) */
/*-------------------------------------------------------------------*/
typedef struct _QDIO_SLSB {
/*000*/ BYTE slsbe[128]; /* Storage Block Address List entry */
#define SLSBE_OWNER 0xC0 /* Owner Mask */
#define SLSBE_OWNER_OS 0x80 /* Control Program is owner */
#define SLSBE_OWNER_CU 0x40 /* Control Unit is owner */
#define SLSBE_TYPE 0x20 /* Buffer type mask */
#define SLSBE_TYPE_INPUT 0x00 /* Input Buffer */
#define SLSBE_TYPE_OUTPUT 0x20 /* Output Buffer */
#define SLSBE_VALID 0x10 /* Buffer Valid */
#define SLSBE_STATE 0x0F /* Buffer state mask */
#define SLSBE_STATE_NOTINIT 0x00 /* Not initialised */
#define SLSBE_STATE_EMPTY 0x01 /* Buffer empty */
#define SLSBE_STATE_PRIMED 0x02 /* Buffer ready */
#define SLSBE_STATE_PENDING 0x03 /* Buffer pending */
#define SLSBE_STATE_HALTED 0x0E /* I/O halted */
#define SLSBE_STATE_ERROR 0x0F /* I/O Error */
#define SLSBE_ERROR 0xFF /* Addressing Error */
#define SLSBE_OUTPUT_PRIMED ( 0 \
| SLSBE_OWNER_CU \
| SLSBE_TYPE_OUTPUT \
| SLSBE_STATE_PRIMED \
)
#define SLSBE_OUTPUT_COMPLETED ( 0 \
| SLSBE_OWNER_OS \
| SLSBE_TYPE_OUTPUT \
| SLSBE_STATE_EMPTY \
)
#define SLSBE_INPUT_EMPTY ( 0 \
| SLSBE_OWNER_CU \
| SLSBE_TYPE_INPUT \
| SLSBE_STATE_EMPTY \
)
#define SLSBE_INPUT_ACKED ( 0 \
| SLSBE_OWNER_OS \
| SLSBE_TYPE_INPUT \
| SLSBE_STATE_EMPTY \
)
#define SLSBE_INPUT_COMPLETED ( 0 \
| SLSBE_OWNER_OS \
| SLSBE_TYPE_INPUT \
| SLSBE_STATE_PRIMED \
)
} QDIO_SLSB;
#endif /*!defined(_QDIO_H)*/
qeth.c
+60 -94
View File
@@ -40,6 +40,7 @@
#include "devtype.h"
#include "chsc.h"
#include "qeth.h"
#include "mpc.h"
#include "tuntap.h"
#define QETH_DEBUG
@@ -163,10 +164,6 @@ static BYTE qeth_immed_commands [256] =
};
#if defined(OSA_FIXED_DEVICE_ORDER)
static const char *osa_devtyp[] = { "Read", "Write", "Data" };
#endif /*defined(OSA_FIXED_DEVICE_ORDER)*/
/*-------------------------------------------------------------------*/
/* STORCHK macro: check storage access & update ref & change bits */
/*-------------------------------------------------------------------*/
@@ -335,12 +332,12 @@ static inline void clr_dsci(DEVBLK *dev, BYTE bits)
/*-------------------------------------------------------------------*/
/* Adapter Command Routine */
/*-------------------------------------------------------------------*/
static void osa_adapter_cmd(DEVBLK *dev, OSA_TH *req_th)
static void osa_adapter_cmd(DEVBLK *dev, MPC_TH *req_th)
{
OSA_GRP *grp = (OSA_GRP*)dev->group->grp_data;
OSA_TH *th = (OSA_TH*)grp->rspbf;
OSA_RRH *rrh;
OSA_PH *ph;
MPC_TH *th = (MPC_TH*)grp->rspbf;
MPC_RRH *rrh;
MPC_PH *ph;
U16 offset;
U16 rqsize;
U32 ackseq;
@@ -353,14 +350,14 @@ U32 ackseq;
if(offset > 0x400)
return;
DUMP(dev, "TH",th,offset);
rrh = (OSA_RRH*)((BYTE*)th+offset);
rrh = (MPC_RRH*)((BYTE*)th+offset);
FETCH_HW(offset,rrh->pduhoff);
if(offset > 0x400)
return;
DUMP(dev, "RRH",rrh,offset);
ph = (OSA_PH*)((BYTE*)rrh+offset);
DUMP(dev, "PH",ph,sizeof(OSA_PH));
ph = (MPC_PH*)((BYTE*)rrh+offset);
DUMP(dev, "PH",ph,sizeof(MPC_PH));
/* Update ACK Sequence Number */
FETCH_FW(ackseq,rrh->ackseq);
@@ -371,16 +368,16 @@ U32 ackseq;
case RRH_TYPE_CM:
{
OSA_PDU *pdu = (OSA_PDU*)(ph+1);
DUMP(dev, "PDU CM",pdu,sizeof(OSA_PDU));
MPC_PDU *pdu = (MPC_PDU*)(ph+1);
DUMP(dev, "PDU CM",pdu,sizeof(MPC_PDU));
UNREFERENCED(pdu);
}
break;
case RRH_TYPE_ULP:
{
OSA_PDU *pdu = (OSA_PDU*)(ph+1);
DUMP(dev, "PDU ULP",pdu,sizeof(OSA_PDU));
MPC_PDU *pdu = (MPC_PDU*)(ph+1);
DUMP(dev, "PDU ULP",pdu,sizeof(MPC_PDU));
switch(pdu->tgt) {
@@ -464,18 +461,18 @@ U32 ackseq;
case RRH_TYPE_IPA:
{
OSA_IPA *ipa = (OSA_IPA*)(ph+1);
DUMP(dev, "IPA",ipa,sizeof(OSA_IPA));
MPC_IPA *ipa = (MPC_IPA*)(ph+1);
DUMP(dev, "IPA",ipa,sizeof(MPC_IPA));
FETCH_HW(offset,ph->pdulen);
if(offset > 0x400)
return;
DUMP(dev, "REQ",(ipa+1),offset-sizeof(OSA_IPA));
DUMP(dev, "REQ",(ipa+1),offset-sizeof(MPC_IPA));
switch(ipa->cmd) {
case IPA_CMD_SETADPPARMS:
{
OSA_IPA_SAP *sap = (OSA_IPA_SAP*)(ipa+1);
MPC_IPA_SAP *sap = (MPC_IPA_SAP*)(ipa+1);
U32 cmd;
FETCH_FW(cmd,sap->cmd);
@@ -563,7 +560,7 @@ U32 ackseq;
case IPA_CMD_SETVMAC:
{
OSA_IPA_MAC *ipa_mac = (OSA_IPA_MAC*)(ipa+1);
MPC_IPA_MAC *ipa_mac = (MPC_IPA_MAC*)(ipa+1);
DBGTRC(dev, "Set VMAC\n");
if(register_mac(ipa_mac->macaddr,MAC_TYPE_UNICST,grp))
@@ -575,7 +572,7 @@ U32 ackseq;
case IPA_CMD_DELVMAC:
{
OSA_IPA_MAC *ipa_mac = (OSA_IPA_MAC*)(ipa+1);
MPC_IPA_MAC *ipa_mac = (MPC_IPA_MAC*)(ipa+1);
DBGTRC(dev, "Del VMAC\n");
if(deregister_mac(ipa_mac->macaddr,MAC_TYPE_UNICST,grp))
@@ -587,7 +584,7 @@ U32 ackseq;
case IPA_CMD_SETGMAC:
{
OSA_IPA_MAC *ipa_mac = (OSA_IPA_MAC*)(ipa+1);
MPC_IPA_MAC *ipa_mac = (MPC_IPA_MAC*)(ipa+1);
DBGTRC(dev, "Set GMAC\n");
if(register_mac(ipa_mac->macaddr,MAC_TYPE_MLTCST,grp))
@@ -599,7 +596,7 @@ U32 ackseq;
case IPA_CMD_DELGMAC:
{
OSA_IPA_MAC *ipa_mac = (OSA_IPA_MAC*)(ipa+1);
MPC_IPA_MAC *ipa_mac = (MPC_IPA_MAC*)(ipa+1);
DBGTRC(dev, "Del GMAC\n");
if(deregister_mac(ipa_mac->macaddr,MAC_TYPE_MLTCST,grp))
@@ -679,8 +676,8 @@ U32 ackseq;
ipa->iid = IPA_IID_ADAPTER | IPA_IID_REPLY;
DUMP(dev, "IPA_HDR RSP",ipa,sizeof(OSA_IPA));
DUMP(dev, "IPA_REQ RSP",(ipa+1),offset-sizeof(OSA_IPA));
DUMP(dev, "IPA_HDR RSP",ipa,sizeof(MPC_IPA));
DUMP(dev, "IPA_REQ RSP",(ipa+1),offset-sizeof(MPC_IPA));
}
/* end case RRH_TYPE_IPA: */
break;
@@ -699,40 +696,23 @@ U32 ackseq;
/*-------------------------------------------------------------------*/
/* Device Command Routine */
/*-------------------------------------------------------------------*/
static void osa_device_cmd(DEVBLK *dev, OSA_IEA *iea)
static void osa_device_cmd(DEVBLK *dev, MPC_IEA *iea)
{
OSA_GRP *grp = (OSA_GRP*)dev->group->grp_data;
OSA_IEAR *iear = (OSA_IEAR*)grp->rspbf;
MPC_IEAR *iear = (MPC_IEAR*)grp->rspbf;
U16 reqtype;
#if defined(OSA_FIXED_DEVICE_ORDER)
U16 datadev;
#endif /*defined(OSA_FIXED_DEVICE_ORDER)*/
memset(iear, 0, sizeof(OSA_IEAR));
memset(iear, 0, sizeof(MPC_IEAR));
FETCH_HW(reqtype, iea->type);
switch(reqtype) {
case IDX_ACT_TYPE_READ:
#if defined(OSA_FIXED_DEVICE_ORDER)
FETCH_HW(datadev, iea->datadev);
if(!IS_OSA_READ_DEVICE(dev))
{
DBGTRC(dev, _("QETH: IDX ACTIVATE READ Invalid for %s Device %4.4x\n"),osa_devtyp[dev->member],dev->devnum);
dev->qdio.idxstate = OSA_IDX_STATE_INACTIVE;
}
else if(datadev != dev->group->memdev[OSA_DATA_DEVICE]->devnum)
{
DBGTRC(dev, _("QETH: IDX ACTIVATE READ Invalid OSA Data Device %d for %s Device %4.4x\n"),datadev,osa_devtyp[dev->member],dev->devnum);
dev->qdio.idxstate = OSA_IDX_STATE_INACTIVE;
}
else
#endif /*defined(OSA_FIXED_DEVICE_ORDER)*/
if((iea->port & IDX_ACT_PORT_MASK) != OSA_PORTNO)
{
DBGTRC(dev, _("QETH: IDX ACTIVATE READ Invalid OSA Port %d for %s Device %4.4x\n"),(iea->port & IDX_ACT_PORT_MASK),dev->devnum);
dev->qdio.idxstate = OSA_IDX_STATE_INACTIVE;
dev->qdio.idxstate = MPC_IDX_STATE_INACTIVE;
}
else
{
@@ -740,29 +720,15 @@ U16 datadev;
iear->flags = IDX_RSP_FLAGS_NOPORTREQ;
STORE_HW(iear->flevel, 0x0201);
dev->qdio.idxstate = OSA_IDX_STATE_ACTIVE;
dev->qdio.idxstate = MPC_IDX_STATE_ACTIVE;
}
break;
case IDX_ACT_TYPE_WRITE:
#if defined(OSA_FIXED_DEVICE_ORDER)
FETCH_HW(datadev, iea->datadev);
if(!IS_OSA_WRITE_DEVICE(dev))
{
DBGTRC(dev, _("QETH: IDX ACTIVATE WRITE Invalid for %s Device %4.4x\n"),osa_devtyp[dev->member],dev->devnum);
dev->qdio.idxstate = OSA_IDX_STATE_INACTIVE;
}
else if(datadev != dev->group->memdev[OSA_DATA_DEVICE]->devnum)
{
DBGTRC(dev, _("QETH: IDX ACTIVATE WRITE Invalid OSA Data Device %d for %s Device %4.4x\n"),datadev,osa_devtyp[dev->member],dev->devnum);
dev->qdio.idxstate = OSA_IDX_STATE_INACTIVE;
}
else
#endif /*defined(OSA_FIXED_DEVICE_ORDER)*/
if((iea->port & IDX_ACT_PORT_MASK) != OSA_PORTNO)
{
DBGTRC(dev, _("QETH: IDX ACTIVATE WRITE Invalid OSA Port %d for device %4.4x\n"),(iea->port & IDX_ACT_PORT_MASK),dev->devnum);
dev->qdio.idxstate = OSA_IDX_STATE_INACTIVE;
dev->qdio.idxstate = MPC_IDX_STATE_INACTIVE;
}
else
{
@@ -770,17 +736,17 @@ U16 datadev;
iear->flags = IDX_RSP_FLAGS_NOPORTREQ;
STORE_HW(iear->flevel, 0x0201);
dev->qdio.idxstate = OSA_IDX_STATE_ACTIVE;
dev->qdio.idxstate = MPC_IDX_STATE_ACTIVE;
}
break;
default:
DBGTRC(dev, _("QETH: IDX ACTIVATE Invalid Request %4.4x for device %4.4x\n"),reqtype,dev->devnum);
dev->qdio.idxstate = OSA_IDX_STATE_INACTIVE;
dev->qdio.idxstate = MPC_IDX_STATE_INACTIVE;
break;
}
grp->rspsz = sizeof(OSA_IEAR);
grp->rspsz = sizeof(MPC_IEAR);
}
@@ -830,17 +796,17 @@ int nobuff = 1;
if(dev->qdio.i_qmask & (0x80000000 >> iq))
{
int ib = dev->qdio.i_bpos[iq];
OSA_SLSB *slsb;
QDIO_SLSB *slsb;
int mb = 128;
slsb = (OSA_SLSB*)(dev->mainstor + dev->qdio.i_slsbla[iq]);
slsb = (QDIO_SLSB*)(dev->mainstor + dev->qdio.i_slsbla[iq]);
while(mb--)
if(slsb->slsbe[ib] == SLSBE_INPUT_EMPTY)
{
OSA_SL *sl = (OSA_SL*)(dev->mainstor + dev->qdio.i_sla[iq]);
QDIO_SL *sl = (QDIO_SL*)(dev->mainstor + dev->qdio.i_sla[iq]);
U64 sa; U32 len; BYTE *buf;
U64 la;
OSA_SBAL *sbal;
QDIO_SBAL *sbal;
int olen = 0; int tlen = 0;
int ns;
int mactype = 0;
@@ -848,7 +814,7 @@ int nobuff = 1;
DBGTRC(dev, _("Input Queue(%d) Buffer(%d)\n"),iq,ib);
FETCH_DW(sa,sl->sbala[ib]);
if(STORCHK(sa,sizeof(OSA_SBAL)-1,dev->qdio.i_slk[iq],STORKEY_REF,dev))
if(STORCHK(sa,sizeof(QDIO_SBAL)-1,dev->qdio.i_slk[iq],STORKEY_REF,dev))
{
slsb->slsbe[ib] = SLSBE_ERROR;
STORAGE_KEY(dev->qdio.i_slsbla[iq], dev) |= (STORKEY_REF|STORKEY_CHANGE);
@@ -859,7 +825,7 @@ int nobuff = 1;
DBGTRC(dev, _("STORCHK ERROR sa(%llx), key(%2.2x)\n"),sa,dev->qdio.i_slk[iq]);
return;
}
sbal = (OSA_SBAL*)(dev->mainstor + sa);
sbal = (QDIO_SBAL*)(dev->mainstor + sa);
for(ns = 0; ns < 16; ns++)
{
@@ -1015,23 +981,23 @@ int mq = dev->qdio.o_qcnt;
if(dev->qdio.o_qmask & (0x80000000 >> oq))
{
int ob = dev->qdio.o_bpos[oq];
OSA_SLSB *slsb;
QDIO_SLSB *slsb;
int mb = 128;
slsb = (OSA_SLSB*)(dev->mainstor + dev->qdio.o_slsbla[oq]);
slsb = (QDIO_SLSB*)(dev->mainstor + dev->qdio.o_slsbla[oq]);
while(mb--)
if(slsb->slsbe[ob] == SLSBE_OUTPUT_PRIMED)
{
OSA_SL *sl = (OSA_SL*)(dev->mainstor + dev->qdio.o_sla[oq]);
QDIO_SL *sl = (QDIO_SL*)(dev->mainstor + dev->qdio.o_sla[oq]);
U64 sa; U32 len; BYTE *buf;
U64 la;
OSA_SBAL *sbal;
QDIO_SBAL *sbal;
int ns;
DBGTRC(dev, _("Output Queue(%d) Buffer(%d)\n"),oq,ob);
FETCH_DW(sa,sl->sbala[ob]);
if(STORCHK(sa,sizeof(OSA_SBAL)-1,dev->qdio.o_slk[oq],STORKEY_REF,dev))
if(STORCHK(sa,sizeof(QDIO_SBAL)-1,dev->qdio.o_slk[oq],STORKEY_REF,dev))
{
slsb->slsbe[ob] = SLSBE_ERROR;
STORAGE_KEY(dev->qdio.o_slsbla[oq], dev) |= (STORKEY_REF|STORKEY_CHANGE);
@@ -1042,7 +1008,7 @@ int mq = dev->qdio.o_qcnt;
DBGTRC(dev, _("STORCHK ERROR sa(%llx), key(%2.2x)\n"),sa,dev->qdio.o_slk[oq]);
return;
}
sbal = (OSA_SBAL*)(dev->mainstor + sa);
sbal = (QDIO_SBAL*)(dev->mainstor + sa);
for(ns = 0; ns < 16; ns++)
{
@@ -1285,7 +1251,7 @@ char qdiostat[80] = {0};
snprintf( buffer, buflen, "QDIO %s%s%sIO[%" I64_FMT "u]"
, (dev->group->acount == OSA_GROUP_SIZE) ? "" : "*Incomplete "
, (dev->scsw.flag2 & SCSW2_Q) ? qdiostat : ""
, (dev->qdio.idxstate == OSA_IDX_STATE_INACTIVE) ? "" : "IDX "
, (dev->qdio.idxstate == MPC_IDX_STATE_INACTIVE) ? "" : "IDX "
, dev->excps
);
@@ -1467,7 +1433,7 @@ int num; /* Number of bytes to move */
/* WRITE */
/*---------------------------------------------------------------*/
{
OSA_HDR *hdr = (OSA_HDR*)iobuf;
MPC_HDR *hdr = (MPC_HDR*)iobuf;
U16 ddc;
if(!grp->rspsz)
@@ -1476,9 +1442,9 @@ int num; /* Number of bytes to move */
obtain_lock(&grp->qlock);
if(ddc == IDX_ACT_DDC)
osa_device_cmd(dev,(OSA_IEA*)iobuf);
osa_device_cmd(dev,(MPC_IEA*)iobuf);
else
osa_adapter_cmd(dev, (OSA_TH*)iobuf);
osa_adapter_cmd(dev, (MPC_TH*)iobuf);
release_lock(&grp->qlock);
signal_condition(&grp->qcond);
@@ -1517,7 +1483,7 @@ int num; /* Number of bytes to move */
}
else
{
if(dev->qdio.idxstate == OSA_IDX_STATE_ACTIVE)
if(dev->qdio.idxstate == MPC_IDX_STATE_ACTIVE)
{
wait_condition(&grp->qcond, &grp->qlock);
if(grp->rspsz)
@@ -1686,8 +1652,8 @@ int num; /* Number of bytes to move */
/* ESTABLISH QUEUES */
/*---------------------------------------------------------------*/
{
OSA_QDR *qdr = (OSA_QDR*)iobuf;
OSA_QDES0 *qdes;
QDIO_QDR *qdr = (QDIO_QDR*)iobuf;
QDIO_QDES0 *qdes;
int accerr;
int i;
@@ -1697,9 +1663,9 @@ int num; /* Number of bytes to move */
FETCH_DW(dev->qdio.qiba,qdr->qiba);
dev->qdio.qibk = qdr->qkey & 0xF0;
if(!(accerr = STORCHK(dev->qdio.qiba,sizeof(OSA_QIB)-1,dev->qdio.qibk,STORKEY_CHANGE,dev)))
if(!(accerr = STORCHK(dev->qdio.qiba,sizeof(QDIO_QIB)-1,dev->qdio.qibk,STORKEY_CHANGE,dev)))
{
OSA_QIB *qib = (OSA_QIB*)(dev->mainstor + dev->qdio.qiba);
QDIO_QIB *qib = (QDIO_QIB*)(dev->mainstor + dev->qdio.qiba);
qib->ac |= QIB_AC_PCI; // Incidate PCI on output is supported
#if defined(_FEATURE_QEBSM)
if(FACILITY_ENABLED_DEV(QEBSM))
@@ -1719,10 +1685,10 @@ int num; /* Number of bytes to move */
dev->qdio.i_sbalk[i] = qdes->keyp2 & 0xF0;
dev->qdio.i_slsblk[i] = (qdes->keyp2 << 4) & 0xF0;
accerr |= STORCHK(dev->qdio.i_slsbla[i],sizeof(OSA_SLSB)-1,dev->qdio.i_slsblk[i],STORKEY_CHANGE,dev);
accerr |= STORCHK(dev->qdio.i_sla[i],sizeof(OSA_SL)-1,dev->qdio.i_slk[i],STORKEY_REF,dev);
accerr |= STORCHK(dev->qdio.i_slsbla[i],sizeof(QDIO_SLSB)-1,dev->qdio.i_slsblk[i],STORKEY_CHANGE,dev);
accerr |= STORCHK(dev->qdio.i_sla[i],sizeof(QDIO_SL)-1,dev->qdio.i_slk[i],STORKEY_REF,dev);
qdes = (OSA_QDES0*)((BYTE*)qdes+(qdr->iqdsz<<2));
qdes = (QDIO_QDES0*)((BYTE*)qdes+(qdr->iqdsz<<2));
}
for(i = 0; i < dev->qdio.o_qcnt; i++)
@@ -1735,16 +1701,16 @@ int num; /* Number of bytes to move */
dev->qdio.o_sbalk[i] = qdes->keyp2 & 0xF0;
dev->qdio.o_slsblk[i] = (qdes->keyp2 << 4) & 0xF0;
accerr |= STORCHK(dev->qdio.o_slsbla[i],sizeof(OSA_SLSB)-1,dev->qdio.o_slsblk[i],STORKEY_CHANGE,dev);
accerr |= STORCHK(dev->qdio.o_sla[i],sizeof(OSA_SL)-1,dev->qdio.o_slk[i],STORKEY_REF,dev);
accerr |= STORCHK(dev->qdio.o_slsbla[i],sizeof(QDIO_SLSB)-1,dev->qdio.o_slsblk[i],STORKEY_CHANGE,dev);
accerr |= STORCHK(dev->qdio.o_sla[i],sizeof(QDIO_SL)-1,dev->qdio.o_slk[i],STORKEY_REF,dev);
qdes = (OSA_QDES0*)((BYTE*)qdes+(qdr->oqdsz<<2));
qdes = (QDIO_QDES0*)((BYTE*)qdes+(qdr->oqdsz<<2));
}
/* Calculate residual byte count */
num = (count < sizeof(OSA_QDR)) ? count : sizeof(OSA_QDR);
num = (count < sizeof(QDIO_QDR)) ? count : sizeof(QDIO_QDR);
*residual = count - num;
if (count < sizeof(OSA_QDR)) *more = 1;
if (count < sizeof(QDIO_QDR)) *more = 1;
if(!accerr)
{
qeth.h
+17 -593
View File
@@ -29,29 +29,6 @@
#define OSA_PORTNO 0
#if defined(OSA_FIXED_DEVICE_ORDER)
/*-------------------------------------------------------------------*/
/* OSA Relative Device Numbers */
/*-------------------------------------------------------------------*/
#define OSA_READ_DEVICE 0
#define OSA_WRITE_DEVICE 1
#define OSA_DATA_DEVICE 2
#define _IS_OSA_TYPE_DEVICE(_dev, _type) \
((_dev)->member == (_type))
#define IS_OSA_READ_DEVICE(_dev) \
_IS_OSA_TYPE_DEVICE((_dev),OSA_READ_DEVICE)
#define IS_OSA_WRITE_DEVICE(_dev) \
_IS_OSA_TYPE_DEVICE((_dev),OSA_WRITE_DEVICE)
#define IS_OSA_DATA_DEVICE(_dev) \
_IS_OSA_TYPE_DEVICE((_dev),OSA_DATA_DEVICE)
#endif /*defined(OSA_FIXED_DEVICE_ORDER)*/
/*-------------------------------------------------------------------*/
/* Number of Devices per OSA Adapter */
/*-------------------------------------------------------------------*/
@@ -70,7 +47,7 @@
/*-------------------------------------------------------------------*/
/* Convert Subchannel Token to IO ID (LCSS & SSID) */
/*-------------------------------------------------------------------*/
#if 1 /* 1 means token != ssid, or 0 means token == ioid */
#if 1 /* 1 means token != ioid, or 0 means token == ioid */
#define TKN2IOID(_token) (~(_token))
#define IOID2TKN(_ioid) (~(_ioid))
#else
@@ -79,17 +56,6 @@
#endif
typedef struct _OSA_MAC {
BYTE addr[6];
int type;
#define MAC_TYPE_NONE 0x00
#define MAC_TYPE_BRDCST 0x01
#define MAC_TYPE_UNICST 0x02
#define MAC_TYPE_MLTCST 0x04
#define MAC_TYPE_ANY 0x0F
} OSA_MAC;
/*-------------------------------------------------------------------*/
/* OSA Node Element Descriptor */
/*-------------------------------------------------------------------*/
@@ -121,6 +87,7 @@ typedef struct _NED {
#define NODE_CLMT 8
#define NODE_CCTCA 9
#define NODE_CSWIT 10
#define NODE_CCTRL 11
/*003*/ BYTE ua;
/*004*/ BYTE devtype[6];
/*00A*/ BYTE model[3];
@@ -149,57 +116,24 @@ typedef struct _NED {
/*-------------------------------------------------------------------*/
/* OSA Device Structure */
/* OSA CCW Assignments */
/*-------------------------------------------------------------------*/
typedef struct _QDIO_DEV {
unsigned rxcnt; /* Receive count */
unsigned txcnt; /* Transmit count */
#define OSA_RCD 0xFA
#define OSA_EQ 0x1B
#define OSA_AQ 0x1F
#define OSA_SII 0x81
#define OSA_RNI 0x82
int idxstate; /* IDX state */
#define OSA_IDX_STATE_INACTIVE 0x00
#define OSA_IDX_STATE_ACTIVE 0x01
int thinint; /* Thin Interrupts on PCI */
int i_qcnt; /* Input Queue Count */
int i_qpos; /* Current Queue Position */
int i_bpos[QDIO_MAXQ]; /* Current Buffer Position */
int o_qcnt; /* Output Queue Count */
int o_qpos; /* Current Queue Position */
int o_bpos[QDIO_MAXQ]; /* Current Buffer Position */
U32 i_qmask; /* Input Queue Mask */
U32 o_qmask; /* Output Queue Mask */
BYTE i_slibk[QDIO_MAXQ]; /* Input SLIB Key */
BYTE i_slk[QDIO_MAXQ]; /* Input Storage List Key */
BYTE i_sbalk[QDIO_MAXQ]; /* Input SBAL Key */
BYTE i_slsblk[QDIO_MAXQ]; /* Input SLSB Key */
U64 i_sliba[QDIO_MAXQ]; /* Input SLIB Address */
U64 i_sla[QDIO_MAXQ]; /* Input Storage List Address */
U64 i_slsbla[QDIO_MAXQ]; /* Input SLSB Address */
BYTE o_slibk[QDIO_MAXQ]; /* Output SLIB Key */
BYTE o_slk[QDIO_MAXQ]; /* Output Storage List Key */
BYTE o_sbalk[QDIO_MAXQ]; /* Output SBAL Key */
BYTE o_slsblk[QDIO_MAXQ]; /* Output SLSB Key */
U64 o_sliba[QDIO_MAXQ]; /* Output SLIB Address */
U64 o_sla[QDIO_MAXQ]; /* Output Storage List Address */
U64 o_slsbla[QDIO_MAXQ]; /* Output SLSB Address */
BYTE qibk; /* Queue Information Block Key */
U64 qiba; /* Queue Information Block Address */
U64 alsi; /* Adapter Local Summ Indicator */
#define ALSI_ERROR 0x80 /* ZZ TO BE CONFIRMED */
U64 dsci; /* Device status change Indicator */
#define DSCI_IOCOMP 0x01 /* ZZ TO BE CONFIRMED */
BYTE ks; /* alsi storage key */
BYTE kc; /* dsci storage key */
} QDIO_DEV;
typedef struct _OSA_MAC {
BYTE addr[6];
int type;
#define MAC_TYPE_NONE 0x00
#define MAC_TYPE_BRDCST 0x01
#define MAC_TYPE_UNICST 0x02
#define MAC_TYPE_MLTCST 0x04
#define MAC_TYPE_ANY 0x0F
} OSA_MAC;
/*-------------------------------------------------------------------*/
@@ -237,516 +171,6 @@ typedef struct _OSA_GRP {
} OSA_GRP;
/*-------------------------------------------------------------------*/
/* OSA CCW Assignments */
/*-------------------------------------------------------------------*/
#define OSA_RCD 0xFA
#define OSA_EQ 0x1B
#define OSA_AQ 0x1F
#define OSA_SII 0x81
#define OSA_RNI 0x82
/*-------------------------------------------------------------------*/
/* Queue Descriptor Entry (Format 0) */
/*-------------------------------------------------------------------*/
typedef struct _OSA_QDES0 {
/*000*/ DBLWRD sliba; /* Storage List Info Block Address */
/*008*/ DBLWRD sla; /* Storage List Address */
/*010*/ DBLWRD slsba; /* Storage List State Block Address */
/*018*/ FWORD resv018;
/*01C*/ BYTE keyp1; /* Access keys for SLIB and SL */
#define QDES_KEYP1_A_SLIB 0xF0
#define QDES_KEYP1_A_SL 0x0F
/*01D*/ BYTE keyp2; /* Access keys for SBALs ad SLSB */
#define QDES_KEYP2_A_SBAL 0xF0
#define QDES_KEYP2_A_SLSB 0x0F
/*01E*/ HWORD resv01e;
} OSA_QDES0;
/*-------------------------------------------------------------------*/
/* Queue Descriptor Record (QDR) */
/*-------------------------------------------------------------------*/
typedef struct _OSA_QDR {
/*000*/ BYTE qfmt; /* Queue Format */
/*001*/ BYTE pfmt; /* Model Dependent Parameter Format */
/*002*/ BYTE resv002;
/*003*/ BYTE ac; /* Adapter Characteristics */
/*004*/ BYTE resv004;
/*005*/ BYTE iqdcnt; /* Input Queue Descriptor Count */
/*006*/ BYTE resv006;
/*007*/ BYTE oqdcnt; /* Output Queue Descriptor Count */
/*008*/ BYTE resv008;
/*009*/ BYTE iqdsz; /* Input Queue Descriptor Size */
/*00A*/ BYTE resv00a;
/*00B*/ BYTE oqdsz; /* Output Queue Descriptor Size */
/*00C*/ FWORD resv00c[9];
/*030*/ DBLWRD qiba; /* Queue Information Block Address */
/*038*/ FWORD resv038;
/*03C*/ BYTE qkey; /* Queue Information Block Key */
/*03D*/ BYTE resv03d[3];
/*040*/ OSA_QDES0 qdf0[126]; /* Format 0 Queue Descriptors */
} OSA_QDR;
/*-------------------------------------------------------------------*/
/* Queue Information Block (QIB) */
/*-------------------------------------------------------------------*/
typedef struct _OSA_QIB {
/*000*/ BYTE qfmt; /* Queue Format */
/*001*/ BYTE pfmt; /* Parameter Format */
#define QID_PFMT_QETH 0x00
/*002*/ BYTE rflags; /* Flags */
#define QIB_RFLAGS_QEBSM 0x80
/*003*/ BYTE ac; /* Adapter Characteristics */
#define QIB_AC_PCI 0x40
/*004*/ FWORD resv004;
/*008*/ DBLWRD isliba; /* Input SLIB queue address */
/*010*/ DBLWRD osliba; /* Output SLIB queue address */
/*018*/ FWORD resv018;
/*01C*/ FWORD resv01c;
/*020*/ BYTE ebcnam[8]; /* Adapter ID in EBCDIC */
/*028*/ BYTE resv028[88];
/*080*/ BYTE parm[128]; /* Model Dependent Parameters */
} OSA_QIB;
/*-------------------------------------------------------------------*/
/* Storage List Information Block (SLIB) */
/*-------------------------------------------------------------------*/
typedef struct _OSA_SLIB {
/*000*/ DBLWRD nsliba; /* Next SLIB in queue */
/*008*/ DBLWRD sla; /* Storage List Address */
/*010*/ DBLWRD slsba; /* Storage List State Block Address */
/*018*/ BYTE resv018[1000];
/*400*/ DBLWRD slibe[128]; /* Storage List Info Block Entry */
} OSA_SLIB;
/*-------------------------------------------------------------------*/
/* Storage List (SL) */
/*-------------------------------------------------------------------*/
typedef struct _OSA_SL {
/*000*/ DBLWRD sbala[128]; /* Storage Block Address List address*/
} OSA_SL;
/*-------------------------------------------------------------------*/
/* Storage Block Address List Entry (SBALE) */
/*-------------------------------------------------------------------*/
typedef struct _OSA_SBALE {
/*000*/ BYTE flags[4]; /* Flags */
#define SBAL_FLAGS0_LAST_ENTRY 0x40
#define SBAL_FLAGS0_CONTIGUOUS 0x20
#define SBAL_FLAGS0_FRAG_MASK 0x0C
#define SBAL_FLAGS0_FRAG_FIRST 0x04
#define SBAL_FLAGS0_FRAG_MIDDLE 0x08
#define SBAL_FLAGS0_FRAG_LAST 0x0C
#define SBAL_FLAGS1_PCI_REQ 0x40
/*004*/ FWORD length; /* Storage length */
/*008*/ DBLWRD addr; /* Storage Address */
} OSA_SBALE;
/*-------------------------------------------------------------------*/
/* Storage Block Address List (SBAL) */
/*-------------------------------------------------------------------*/
typedef struct _OSA_SBAL {
/*000*/ OSA_SBALE sbale[16]; /* Storage Block Address List entry */
} OSA_SBAL;
/*-------------------------------------------------------------------*/
/* Storage List State Block (SLSB) */
/*-------------------------------------------------------------------*/
typedef struct _OSA_SLSB {
/*000*/ BYTE slsbe[128]; /* Storage Block Address List entry */
#define SLSBE_OWNER 0xC0 /* Owner Mask */
#define SLSBE_OWNER_OS 0x80 /* Control Program is owner */
#define SLSBE_OWNER_CU 0x40 /* Control Unit is owner */
#define SLSBE_TYPE 0x20 /* Buffer type mask */
#define SLSBE_TYPE_INPUT 0x00 /* Input Buffer */
#define SLSBE_TYPE_OUTPUT 0x20 /* Output Buffer */
#define SLSBE_VALID 0x10 /* Buffer Valid */
#define SLSBE_STATE 0x0F /* Buffer state mask */
#define SLSBE_STATE_NOTINIT 0x00 /* Not initialised */
#define SLSBE_STATE_EMPTY 0x01 /* Buffer empty */
#define SLSBE_STATE_PRIMED 0x02 /* Buffer ready */
#define SLSBE_STATE_PENDING 0x03 /* Buffer pending */
#define SLSBE_STATE_HALTED 0x0E /* I/O halted */
#define SLSBE_STATE_ERROR 0x0F /* I/O Error */
#define SLSBE_ERROR 0xFF /* Addressing Error */
#define SLSBE_OUTPUT_PRIMED ( 0 \
| SLSBE_OWNER_CU \
| SLSBE_TYPE_OUTPUT \
| SLSBE_STATE_PRIMED \
)
#define SLSBE_OUTPUT_COMPLETED ( 0 \
| SLSBE_OWNER_OS \
| SLSBE_TYPE_OUTPUT \
| SLSBE_STATE_EMPTY \
)
#define SLSBE_INPUT_EMPTY ( 0 \
| SLSBE_OWNER_CU \
| SLSBE_TYPE_INPUT \
| SLSBE_STATE_EMPTY \
)
#define SLSBE_INPUT_ACKED ( 0 \
| SLSBE_OWNER_OS \
| SLSBE_TYPE_INPUT \
| SLSBE_STATE_EMPTY \
)
#define SLSBE_INPUT_COMPLETED ( 0 \
| SLSBE_OWNER_OS \
| SLSBE_TYPE_INPUT \
| SLSBE_STATE_PRIMED \
)
} OSA_SLSB;
/*-------------------------------------------------------------------*/
/* Header for OSA command frames */
/*-------------------------------------------------------------------*/
typedef struct _OSA_HDR {
/*000*/ HWORD resv000; /* */
/*002*/ HWORD ddc; /* Device Directed Command */
#define IDX_ACT_DDC 0x8000
/*004*/ FWORD thsn; /* Transport Header Sequence Number */
} OSA_HDR;
/*-------------------------------------------------------------------*/
/* Identification Exchange Activate */
/*-------------------------------------------------------------------*/
typedef struct _OSA_IEA {
/*000*/ OSA_HDR hdr;
/*008*/ HWORD type; /* IDX_ACT type (read or write) */
#define IDX_ACT_TYPE_READ 0x1901
#define IDX_ACT_TYPE_WRITE 0x1501
/*00A*/ BYTE resv00a; /* */
#define IDX_ACT_RESV00A 0x01
/*00B*/ BYTE port; /* Port number (bit 0 set) */
#define IDX_ACT_PORT_MASK 0x3F
#define IDX_ACT_PORT_ACTIVATE 0x80
#define IDX_ACT_PORT_STANDBY 0x40
/*00C*/ FWORD token; /* Issuer token */
/*010*/ HWORD flevel; /* Function level */
#define IDX_ACT_FLEVEL_READ 0x0000
#define IDX_ACT_FLEVEL_WRITE 0xFFFF
/*012*/ FWORD uclevel; /* Microcode level */
/*016*/ BYTE dataset[8]; /* Portname */
/*01E*/ HWORD datadev; /* Data Device Number */
/*020*/ BYTE ddcua; /* Data Device Control Unit Address */
/*021*/ BYTE ddua; /* Data Device Unit Address */
} OSA_IEA;
/*-------------------------------------------------------------------*/
/* Identification Exchange Activate Response */
/*-------------------------------------------------------------------*/
typedef struct _OSA_IEAR {
/*000*/ HWORD resv000; /* */
/*002*/ BYTE cmd; /* Response code */
#define IDX_RSP_CMD_MASK 0xC0
#define IDX_RSP_CMD_TERM 0xC0 /* IDX_TERMINATE received */
/*003*/ BYTE resv003; /* */
/*004*/ BYTE reason; /* Reason code */
#define IDX_RSP_REASON_INVPORT 0x22
/*005*/ BYTE resv005[3]; /* */
/*008*/ BYTE resp; /* Response code */
#define IDX_RSP_RESP_MASK 0x03
#define IDX_RSP_RESP_OK 0x02
/*009*/ BYTE cause; /* Negative response cause code */
#define IDX_RSP_CAUSE_INUSE 0x19
/*00A*/ BYTE resv010; /* */
/*00B*/ BYTE flags; /* Flags */
#define IDX_RSP_FLAGS_NOPORTREQ 0x80
/*00C*/ FWORD token; /* Issues rm_r token */
/*010*/ HWORD flevel; /* Funtion level */
/*012*/ FWORD uclevel; /* Microcode level */
} OSA_IEAR;
/*-------------------------------------------------------------------*/
/* Transport Header */
/*-------------------------------------------------------------------*/
typedef struct _OSA_TH {
/*000*/ OSA_HDR hdr;
/*008*/ HWORD resv008; /* */
/*00A*/ HWORD rroff; /* Offset to request/response struct */
/*00C*/ HWORD resv00c; /* */
/*00E*/ HWORD rrlen; /* Length of request/response struct */
/*010*/ FWORD end; /* X'10000001' */
} OSA_TH;
/*-------------------------------------------------------------------*/
/* Request/Response Header */
/*-------------------------------------------------------------------*/
typedef struct _OSA_RRH {
/*000*/ FWORD resv000; /* */
/*004*/ BYTE type; /* Request type */
#define RRH_TYPE_CM 0x81
#define RRH_TYPE_ULP 0x41
#define RRH_TYPE_IPA 0xC1
/*005*/ BYTE proto; /* Protocol type */
#define RRH_PROTO_L2 0x08
#define RRH_PROTO_L3 0x03
#define RRH_PROTO_NCP 0x0A
#define RRH_PROTO_UNK 0x7E
/*006*/ HWORD unkn006; /* X'0001' */
/*008*/ FWORD pduseq; /* PDU Sequence Number */
/*00C*/ FWORD ackseq; /* ACK Sequence Number */
/*010*/ HWORD pduhoff; /* Offset to PDU Header */
/*012*/ HWORD pduhlen; /* Length of PDU Header */
/*014*/ BYTE resv014; /* */
/*015*/ HWORD reqlen; /* Request length */
/*017*/ BYTE unkn016; /* X'05' */
/*018*/ FWORD token; /* */
/*01C*/ FWORD resv020; /* */
/*020*/ FWORD resv024; /* */
} OSA_RRH;
/*-------------------------------------------------------------------*/
/* Protocol Data Unit Header */
/*-------------------------------------------------------------------*/
typedef struct _OSA_PH {
/*000*/ HWORD type; /* */
/*002*/ HWORD pdulen; /* Length of request */
/*004*/ HWORD resv004; /* */
/*006*/ HWORD hdrlen; /* Total Header lenght */
} OSA_PH;
/*-------------------------------------------------------------------*/
/* Protocol Data Unit */
/*-------------------------------------------------------------------*/
typedef struct _OSA_PDU {
/*000*/ HWORD len; /* */
/*002*/ BYTE tgt; /* Command target */
#define PDU_TGT_OSA 0x41
#define PDU_TGT_QDIO 0x43
/*003*/ BYTE cmd; /* Command */
#define PDU_CMD_ENABLE 0x02
#define PDU_CMD_SETUP 0x04
#define PDU_CMD_ACTIVATE 0x60
/*004*/ HWORD rlen; /* Request length */
/*006*/ HWORD resv006; /* */
/*008*/ FWORD resv008; /* */
/*00C*/ HWORD ilen; /* */
/*00E*/ BYTE unkn00e; /* */
/*00F*/ BYTE unkn00f; /* */
/*010*/ BYTE proto; /* */
#define PDU_PROTO_L2 0x08
#define PDU_PROTO_L3 0x03
#define PDU_PROTO_NCP 0x0A
#define PDU_PROTO_UNK 0x7E
// ZZ INCOMPLETE
} OSA_PDU;
/*-------------------------------------------------------------------*/
/* IP Assist Header */
/*-------------------------------------------------------------------*/
typedef struct _OSA_IPA {
/*000*/ BYTE cmd; /* Command */
/*001*/ BYTE iid; /* Initator Identifier */
#define IPA_IID_HOST 0x00
#define IPA_IID_ADAPTER 0x01
#define IPA_IID_REPLY 0x80
/*002*/ HWORD seq; /* Sequence number */
/*004*/ HWORD rc; /* Return Code */
#define IPA_RC_OK IPA_RC_SUCCESS
/*006*/ BYTE at; /* Adapter Type */
#define IPA_AT_ANY 0x01
/*007*/ BYTE port; /* OSA Port Number */
/*008*/ BYTE lvl; /* OSA Level */
#define IPA_LVL_ANY 0x01
#define IPA_LVL_L2 0x02
/*009*/ BYTE cnt; /* Parameter Count */
/*00A*/ HWORD proto; /* Protocol */
#define IPA_PROTO_ANY 0x0000
#define IPA_PROTO_IPV4 0x0004
#define IPA_PROTO_IPV6 0x0006
/*00C*/ FWORD ipas; /* Supported IP Assist mask */
/*010*/ FWORD ipae; /* Enabled IP Assist mask */
} OSA_IPA;
#define IPA_ARP_PROCESSING 0x00000001L
#define IPA_INBOUND_CHECKSUM 0x00000002L
#define IPA_OUTBOUND_CHECKSUM 0x00000004L
#define IPA_IP_FRAGMENTATION 0x00000008L
#define IPA_FILTERING 0x00000010L
#define IPA_IPV6 0x00000020L
#define IPA_MULTICASTING 0x00000040L
#define IPA_IP_REASSEMBLY 0x00000080L
#define IPA_QUERY_ARP_COUNTERS 0x00000100L
#define IPA_QUERY_ARP_ADDR_INFO 0x00000200L
#define IPA_SETADAPTERPARMS 0x00000400L
#define IPA_VLAN_PRIO 0x00000800L
#define IPA_PASSTHRU 0x00001000L
#define IPA_FLUSH_ARP_SUPPORT 0x00002000L
#define IPA_FULL_VLAN 0x00004000L
#define IPA_INBOUND_PASSTHRU 0x00008000L
#define IPA_SOURCE_MAC 0x00010000L
#define IPA_OSA_MC_ROUTER 0x00020000L
#define IPA_QUERY_ARP_ASSIST 0x00040000L
#define IPA_INBOUND_TSO 0x00080000L
#define IPA_OUTBOUND_TSO 0x00100000L
#define IPA_SUPP ( 0 \
| IPA_PASSTHRU \
| IPA_INBOUND_PASSTHRU \
)
#define IPA_CMD_STARTLAN 0x01 /* Start LAN operations */
#define IPA_CMD_STOPLAN 0x02 /* Stop LAN operations */
#define IPA_CMD_SETVMAC 0x21 /* Set Layer-2 MAC address */
#define IPA_CMD_DELVMAC 0x22 /* Delete Layer-2 MAC address */
#define IPA_CMD_SETGMAC 0x23 /* Set Layer-2 Group Multicast addr */
#define IPA_CMD_DELGMAC 0x24 /* Del Layer-2 Group Multicast addr */
#define IPA_CMD_SETVLAN 0x25 /* Set Layer-2 VLAN */
#define IPA_CMD_DELVLAN 0x26 /* Delete Layer-2 VLAN */
#define IPA_CMD_SETCCID 0x41 /* */
#define IPA_CMD_DELCCID 0x42 /* */
#define IPA_CMD_MODCCID 0x43 /* */
#define IPA_CMD_SETIP 0xB1 /* Set Layer-3 IP unicast address */
#define IPA_CMD_QIPASSIST 0xB2 /* Query Layer-3 IP assist capability*/
#define IPA_CMD_SETASSPARMS 0xB3 /* Set Layer-3 IP assist parameters */
#define IPA_CMD_SETIPM 0xB4 /* Set Layer-3 IP multicast address */
#define IPA_CMD_DELIPM 0xB5 /* Delete Layer-3 IP multicast addr */
#define IPA_CMD_SETRTG 0xB6 /* Set Layer-3 routing information */
#define IPA_CMD_DELIP 0xB7 /* Delete Layer-3 IP unicast addr */
#define IPA_CMD_SETADPPARMS 0xB8 /* Various adapter directed sub-cmds*/
#define IPA_CMD_SETDIAGASS 0xB9 /* Set Layer-3 diagnostic assists */
#define IPA_CMD_CREATEADDR 0xC3 /* Create L3 IPv6 addr from L2 MAC */
#define IPA_CMD_DESTROYADDR 0xC4 /* Destroy L3 IPv6 addr from L2 MAC */
#define IPA_CMD_REGLCLADDR 0xD1 /* */
#define IPA_CMD_UNREGLCLADDR 0xD2 /* */
#define IPA_RC_SUCCESS 0x0000
#define IPA_RC_NOTSUPP 0x0001
#define IPA_RC_IP_TABLE_FULL 0x0002
#define IPA_RC_UNKNOWN_ERROR 0x0003
#define IPA_RC_UNSUPPORTED_COMMAND 0x0004
#define IPA_RC_TRACE_ALREADY_ACTIVE 0x0005
#define IPA_RC_INVALID_FORMAT 0x0006
#define IPA_RC_DUP_IPV6_REMOTE 0x0008
#define IPA_RC_DUP_IPV6_HOME 0x0010
#define IPA_RC_UNREGISTERED_ADDR 0x0011
#define IPA_RC_NO_ID_AVAILABLE 0x0012
#define IPA_RC_ID_NOT_FOUND 0x0013
#define IPA_RC_INVALID_IP_VERSION 0x0020
#define IPA_RC_LAN_FRAME_MISMATCH 0x0040
#define IPA_RC_L2_UNSUPPORTED_CMD 0x2003
#define IPA_RC_L2_DUP_MAC 0x2005
#define IPA_RC_L2_ADDR_TABLE_FULL 0x2006
#define IPA_RC_L2_DUP_LAYER3_MAC 0x200a
#define IPA_RC_L2_GMAC_NOT_FOUND 0x200b
#define IPA_RC_L2_MAC_NOT_AUTH_BY_HYP 0x200c
#define IPA_RC_L2_MAC_NOT_AUTH_BY_ADP 0x200d
#define IPA_RC_L2_MAC_NOT_FOUND 0x2010
#define IPA_RC_L2_INVALID_VLAN_ID 0x2015
#define IPA_RC_L2_DUP_VLAN_ID 0x2016
#define IPA_RC_L2_VLAN_ID_NOT_FOUND 0x2017
#define IPA_RC_DATA_MISMATCH 0xe001
#define IPA_RC_INVALID_MTU_SIZE 0xe002
#define IPA_RC_INVALID_LANTYPE 0xe003
#define IPA_RC_INVALID_LANNUM 0xe004
#define IPA_RC_DUPLICATE_IP_ADDRESS 0xe005
#define IPA_RC_IP_ADDR_TABLE_FULL 0xe006
#define IPA_RC_LAN_PORT_STATE_ERROR 0xe007
#define IPA_RC_SETIP_NO_STARTLAN 0xe008
#define IPA_RC_SETIP_ALREADY_RECEIVED 0xe009
#define IPA_RC_IP_ADDR_ALREADY_USED 0xe00a
#define IPA_RC_MC_ADDR_NOT_FOUND 0xe00b
#define IPA_RC_SETIP_INVALID_VERSION 0xe00d
#define IPA_RC_UNSUPPORTED_SUBCMD 0xe00e
#define IPA_RC_ARP_ASSIST_NO_ENABLE 0xe00f
#define IPA_RC_PRIMARY_ALREADY_DEFINED 0xe010
#define IPA_RC_SECOND_ALREADY_DEFINED 0xe011
#define IPA_RC_INVALID_SETRTG_INDICATOR 0xe012
#define IPA_RC_MC_ADDR_ALREADY_DEFINED 0xe013
#define IPA_RC_LAN_OFFLINE 0xe080
#define IPA_RC_INVALID_IP_VERSION2 0xf001
#define IPA_RC_FFFF 0xffff
/*-------------------------------------------------------------------*/
/* MAC request */
/*-------------------------------------------------------------------*/
typedef struct _OSA_IPA_MAC {
/*000*/ FWORD maclen; /* Length of MAC Address */
/*004*/ BYTE macaddr[FLEXIBLE_ARRAY]; /* MAC Address */
} OSA_IPA_MAC;
/*-------------------------------------------------------------------*/
/* Set Adapter Parameters */
/*-------------------------------------------------------------------*/
typedef struct _OSA_IPA_SAP {
/*000*/ FWORD suppcm; /* Supported subcommand mask */
#define IPA_SAP_QUERY 0x00000001L
#define IPA_SAP_SETMAC 0x00000002L
#define IPA_SAP_SETGADR 0x00000004L
#define IPA_SAP_SETFADR 0x00000008L
#define IPA_SAP_SETAMODE 0x00000010L
#define IPA_SAP_SETCFG 0x00000020L
#define IPA_SAP_SETCFGE 0x00000040L
#define IPA_SAP_BRDCST 0x00000080L
#define IPA_SAP_OSAMSG 0x00000100L
#define IPA_SAP_SETSNMP 0x00000200L
#define IPA_SAP_CARDINFO 0x00000400L
#define IPA_SAP_PROMISC 0x00000800L
#define IPA_SAP_SETDIAG 0x00002000L
#define IPA_SAP_SETACCESS 0x00010000L
#define IPA_SAP_SUPP ( 0 \
| IPA_SAP_QUERY \
| IPA_SAP_PROMISC \
)
/*004*/ FWORD resv004; /* */
/*008*/ HWORD cmdlen; /* Subcommand length */
/*00A*/ HWORD resv00a; /* */
/*00C*/ FWORD cmd; /* Subcommand */
/*010*/ HWORD rc; /* Return Code */
/*012*/ BYTE used; /* */
/*013*/ BYTE seqno; /* */
/*014*/ FWORD resv014; /* */
} OSA_IPA_SAP;
/*-------------------------------------------------------------------*/
/* SAP ADP Qeury */
/*-------------------------------------------------------------------*/
typedef struct _SAP_QRY {
/*000*/ FWORD nlan; /* Number of Lan types supported */
/*004*/ BYTE rsp; /* LAN type response */
/*005*/ BYTE resv005[3];
/*008*/ FWORD suppcm; /* Supported commands bit map */
/*00A*/ DBLWRD resv00a;
} SAP_QRY;
/*-------------------------------------------------------------------*/
/* Set Promiscuous Mode on/off */
/*-------------------------------------------------------------------*/
typedef struct _SAP_SPM {
/*000*/ FWORD promisc; /* Promiscuous mode */
#define SAP_PROMISC_ON 0x00000001
#define SAP_PROMISC_OFF 0x00000000
} SAP_SPM;
/*-------------------------------------------------------------------*/
/* OSA Layer 2 Header */
/*-------------------------------------------------------------------*/